JEDEC JEB5-A-1970 Methods of Measurement for Semiconductor Logic Gating Microcircuits《半导体逻辑门微电路测量方法》.pdf

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1、. c- i I EIA JEB5-A 70 3234b00 O003059 4 JANUARY 1070 JEDEC ENGINEERING BULLETIN NO. -5-A METHODS OF MEASUREMENT FOR SEMICONDUCTOR LOGIC GATING MICROCIRCUITS JEDEC Solid State Products Engineering Council EIA JEBS-A 70 m 3234600 O003060 O m 1 METHODS OF MEASUREMENT FOR SEMICONDUCTOR LOGIC GATING MIC

2、ROCIRCUITS JEDEC ENGINEERING BULLETIN NO. 5-A Published by ELECTRONIC INDUSTRIES ASSOCIATION Engineering Department 2001 Eye Street, N.W. Washington, D.C. 20006 Printed in U.S.A. o . EIA JEBS-A 70 m 3234600 00030bL 2 m . - 7 CONTENTS Foreword General Background Minimum DC Characteristics for Interch

3、angeability Definitions Commentary on the Registration Data Format General ahd Logic Maximum Ratings Electrical Characteristics Static DCTL-RTL DTL-TTL ECL Dynamic Format MED-32-1C, “Registration Data, Semiconductar Logic Gating Microcircuit! iii 1 2 2 3 3 3 4 6 9 12 16 Appendix I - e EIA JEBS-A 70

4、W 3234600 O003062 4 W FOREWORD The test methods and other material included herewith are recommended for use in the rating of semiconductor logic gating microcircuits which use the binary states to represent and process logic information. Both static and dynamic meas- urements are covered. These met

5、hods of measurement are equally applicable to monolithic, multichip, film or hybrid device con- struction, whether of silicon, germanium, or other semiconductor material, whether incorporating bipolar or MOS or both types of transistor technology. The purpose of this bulletin is twofold. It is to de

6、scribe recommended tests and test methods, as noted above. intended to assist and instruct those who complete and use the EIA Registration Data format for semiconductor logic gating micro- circuits, MED-32-1C. It is also This document has been prepared by the MED-32 Committee on Active Digital Circu

7、its and has been approved for publication by the EIA Microelectronics Engineering Panel. EIA JEB5-A ?O m 3234600 00030b3 b m GENERAL BACKGROUND For the circuit configurations of semiconductor logic gating micro- circuits which use binary states to represent the digital information, a logical relatio

8、nship exists between input and output. The logical condi- tions can be identified by the electrical parameters measured on the input and output to describe the binary states. to describe the states, but voltage is used most commonly. Voltages or currents may be used The diagram of Figure 1 shows the

9、 state of the output of a gating cir- cuit as a function of the input, using voltages to represent the states. There are certain limits that can be applied to each of the states to identify the acceptable operating regions for a particular design. which is for an inverting logic gate, the output vol

10、tage must be withh the cross-hatched areas for the defined voltages that appear at the input. V1Hmi.n VILIMX, VIHX, and VI-min are the boundaries of these regions, logic gating circuits must couple to each other,the same values apply to input and output. for the input and output voltages under worst

11、 case conditions for any logic gating circuit in a digital system made up of such gates, Thus, on Figure 1, Since the The cross-hatched regions represent the regions of DC stability Output Voltage V max OH - vO VOHmaxL V max TH I I 1 VoLmax 5 V max t IL 1 V min V min OL - IL Input Voltage VI OUTPUT

12、VS INPUT VOLTAGE FOR AN INVERTING LOGIC GATING MICROCIRCUIT Figure 1 VILX is the maximum allowed input LOW level in a logic system; V1Hmi.n is the minimum allowed input HIGH level in a logic system. less than VILmax or greater than VIHmin, but less than VIHmax the output volt- age must be in the cro

13、ss-hatched area, as the maximum HIGH state output can be. age unless the output has an active rather than a resistive pull-up. chosen to be at least as small as a minimum LOW state output can be. erally is zero and is shown so in Figure 1 and used so in the following test condition. For any VI value

14、 VIlImax is chosen to be at least as large It will generally be the supply volt- VILmin is It gen- - -1- EIA JEB5-A 70 m 3239b00 000306Y 8 m MINIMUM DC CHARACTEBISTICS FOR 3NTERCJU“ANEABILLTY In setting the registration format for semiconductor logic gating microcircuits, it was found that a univers

15、al set of “black-box“ specifi- cations could not be settled on without getting very cumbersome. There- fore, the format has been divided according to the type of circuit con- figuration of the logic gating circuit, information is required to assure interchangeability. what is considered the minimum

16、information necessary to describe a logic gate, A certain minimum amount of The format contains The inverting logic function is assumed in most of the format and Transposition of the worst- in the commentary and curves which follow, case conditions for non-inverting logic should be made as appropria

17、te. DEFINITIONS HIGH and LOW Levels The HIGH (H) level is that level which is the most positive of the two logic levels whereas the LOW (L) level is that level which is the most negative of the two logic levels. Positive and Negative Logic the HIGH level and logic ZERO with the LOW level. Positive l

18、ogic identifies the logic ONE with Negative logic identi- fies the logic ONE with the LOW level and the logic ZERO with the HIGH level, Positive Current Conventional currant flow in$o a mtcrocircuit terminal is defined as positive, Maximum Limit For logic levels only, the most positive (least negati

19、ve) limit. The highest-magnitude limit of a range of some quantity. Minimum Limit For logic levels only, the least positive (most negative) limit. The lowest-magnitude limit of a range of some quantity. Logic Gating format, theterm “logic gating“ is used. binatorial logic functions and to exclude se

20、quential logic funtions. latter, because they have memory, are covered by the bistable bulletin and registration data or some extension of it. logic gates inside the registered microcircuit are within the applicabil- ity of this bulletin on logic gating microcircuits, provided that no invert- ing ga

21、tes are cross-coupled (the output of gate A drives an inverting input of gate B and the output of gate B drives an inverting input of gate A) or the equivalent or obtain logic memory in any other manner. In the titles of this bulletin and the registration data This is meant to cover all com- The Thu

22、s all interconnections of For additional definitions, see also EIA format MED-32-1C, “Registration Data, Semiconductor Logic Gating Microcircuit,“ Appendix I. Microelectronics Engineering Bulletin lA, “Recommended Microelectronic Terms and Definitions .“ -2- EIA JEB5-A 70 m 3234b00 00030b5 T m CONME

23、NTARY ON IHE REGISTRATION DATA FORMAT Numbering herein is identical to that used in the MeD-321-1C format for semiconductir logic gating microcircuits, 1.0 GENERAL DESCRIPTIONS 1.1 Type of Device specifies semiconductor material. 1,2 Type of Logic Function and Polarity describes the number of separa

24、te gates within the device and the logic function provided (NANA, AND, NOR, OR, COMBINATIONAL, etc.) and specifies whether positive or neg- ative logic is meant. 1.3 Number of Inpugs identifies all inputs to the device. the number of inputs to each section of the device as well as expand- ing nodes

25、for increasing fan-in or performing other logic functions externally. Number and Type of Outputs describe the number and electrical type (open collector, emitter follower, etc,) of external outputs from each gate, It should be stated if logic can or should not be per- formed by connecting outputs to

26、gether, This includes 1.4 2.0 LOGIC DESCRTPTION The device must be completely described with a logic diagram, logic equations, and a truth table relating inputs to outputs. 2.1 The. Logic Diagram represents the circuit function symbolically. Each terminal (inputs and outputs) must be identified with

27、 letters for ref- erence to the logic equaiion and truth table, The preferred logic symbols are those defined in “Graphic Symbols for Logic Diagrams,“ IEEE Publication No, 91/ANS Y32.14, 2.2 The Logic Equation relates each output to the inputs. must be consistent with the type and polarity of logic

28、function de- scribed in Section 1.2 and the tezminal identification in Section 2.1. This equation 2.3 The Truth Table shows the relations between the HIGH (H) or LOW (L) logic levels of the inputs and outputs. The “HIGH/LOW“ designation should be used in the truth table to avoid any confusion betwee

29、n pos- itive or negative logic notation, Generally every column corresponds to the level of an input or output and every line corresponds to a combination of the input level and the resulting output level or levels, Whenever the level of an input has no influence it should be indicated by the symbol

30、 “X.“ 3.0 MECHANICAL DATA No commentary beyond notes incorporated in the regis- tration data format is necessary. 4.0 MAXIMUM RATINGS A maximum rating is a limiting value of voltage, current or temperature which is to be exceeded only at the risk of permanently altering the characteristics of the mi

31、crocircuit, A combination of maxi- mum ratings cannot normally be permitted simultaneously. a 4.1 Temperature 4,l.l Storage Temperature Range defines the range of environment in which a microcircuit may be stored with no electrical connec- tions to the device. 4.12 Temperature Range under Bias defin

32、es the temperature range In which the microcircuit may.be operated without risk of permanent change. maximum temperature in a system under some fault condition of cooling with supply voltages,still applied, correct logic operation in intended. and the bias conditions must be specified. Bias should r

33、epresent that set of expected extreme continuous operating conditions of supply voltages, input drive, and output loading which result in worst-case power consumption. If the operating frequency has any significant effect on power consumption, a normal operating fre- quency shall be specified. The i

34、ntent of this paragraph is to state the allowable No guarantee of Both the temperature range 4.2 Terminal Voltage and/or Current Terminal Voltage and/or Current defines the maximum voltage and/or current that may be safely applied to each terminal of the microcircuit without risk of permanently alte

35、r- ing any of its characteristics, anteed over a specified temperature range and that this temperature range characteristics under paragraph 5,1,2.2 but not necessarily those spec- ified under paragraph 4.1.2. Each of these maximum values is defined independently of all others. For example, if a max

36、imum power supply voltage is specified at 10 V and a maximum output current is specified to be 50 mA, the 10 V and 50 mA conditions cannot necessarily be applied simultaneously, In addition, if the maximum values specified apply only for certain conditions on other tsrminals, then these relevant con

37、di- tions must also be specified, When maximum ratings are specified for both voltage and current at the same terminal, these maximum values re - not defined independent of one another. Pbr instance, ifa maximum out- put voltage is speciied at 8 V and a maximurn current is specified to be 30mA for t

38、he same output, neither rating may be exceeded in attempting to apply the other. Note that these ratings must be guar- include the temperature extremes specified for electrical 5.0 ELECTRICAL CHARACTERISTICS 5.1 Operating Conditions The notes in the registration data format are sufficient for use an

39、d understanding. No additional commentary is needed, 5.2 Static Characteristics A. For registration of static characteristics, three alternate sequen- ces of tests are provided. circuit types in use: 5.2.1 DCTL, RTT, and RCTL These sequences relate to the three main EIA JEB5-A 70 m 3234600 00030b7 3

40、 m One of these sequences, where applicable to the type of circuit configuration used, should be chosen. For multiple duplicate gates, these tests apply for each gate, For more complex com- binations of gates, these tests should serve as guiding rules in specifying the circuits, Conditions on all te

41、rminals must be specified for each test, B. The first two items in each sequence (5,2.X.1 and 5,2.X.2) are not tests, They are definitions of input logic voltage levels. This is the starting point for the registration of all electrical parameters. They are, by nature, definitions of the maximum and

42、minimum LOW (L) and HIGH (H) voltage levels which will be accepted and recognized by the registered device, These do not appear as parameters in the format, The validity of the definitions is proven by using them as conditions and verifying that they do re- sult in proper logical operation according

43、 to the truth tables of paragraph 2.2. They are used for both Static and Dynamic charac- teristics. Generally, the output levels of a logic gate are intended to be compatible with its input requirements. The logic gate output is intended to drive other logic gates like it- self or other logic elemen

44、ts in the same family having compatible input requirements, Therefore, a relationship generally exists as depicted in Figure 2. G. In the descriptions and comments which follow, for each of the three sequences of tests, the same paragraph numbering is used as that given in the registration data form

45、at, Description of many of the tests is clarified by reference to Figures showing certain electrical characteristics. by “Xs“ and are keyed CO the text by circled numbers, bers are the least significant (right-most) part of the decimal number of the respective test, The test points are located The n

46、um- O iNPUTS Voltage OUTPUTS v max HIGH I- HIGH V OH min OH v max I IL LOW Relatdonship. between Input and Output HIGH and LOW Levels FIGURE 2 -5- EIA JEBS-A 70 M 3234600 00030b8 5 M 5,2.1 Static Characteristics of DCTL-RTL Type Digital Circuitry This section will serve to illustrate the application

47、 of the logic gating format to an REL type gate, with the aid of a transfer characteristic curve which is labeled . with both the EIA standard terminology and the corresponding ter- minology most commonly employed in current RTL literature; see Figure 3, With the aid of this curve the terms can be i

48、nterpreted as follows: This can best be illustrated 5,Z.l.l A: VILmin - TQe minimum voltage that can be applied at the input of an RTL gate, In principle this may be zero volts. In practice;this would normally be output of a heav- ily saturated gate. B: VILmax - The maximum low level voltage that ca

49、n be applied to This is com- the input of an RTL gate and maintain that gate in the logical high state (VOH 2 VoHmin). monly referred to as VOFF in RTL literature. 5.2.1.2 A: VIHmin - The minimum high level voltage that can be applied to an RTL gate to guarantee that the gate output will maintain the logical low condition (VOL 5 VoLmax), This is commonly referred to a V in RTL literature. The purpose of this measurement is to establish the guaranteed value of Iavailable for fanout purposes. This current is normally specified at the VIH required to drive the next gate loa