DLA SMD-5962-95660 REV C-2000 MICROCIRCUIT DIGITAL RADIATION HARDENED ADVANCED CMOS QUAD 2-INPUT EXCLUSIVE OR GATE TTL COMPATIBLE INPUTS MONOLITHIC SILICON《互补金属氧化物半导体数字的四重2输入排外硅单片电.pdf

《DLA SMD-5962-95660 REV C-2000 MICROCIRCUIT DIGITAL RADIATION HARDENED ADVANCED CMOS QUAD 2-INPUT EXCLUSIVE OR GATE TTL COMPATIBLE INPUTS MONOLITHIC SILICON《互补金属氧化物半导体数字的四重2输入排外硅单片电.pdf》由会员分享，可在线阅读，更多相关《DLA SMD-5962-95660 REV C-2000 MICROCIRCUIT DIGITAL RADIATION HARDENED ADVANCED CMOS QUAD 2-INPUT EXCLUSIVE OR GATE TTL COMPATIBLE INPUTS MONOLITHIC SILICON《互补金属氧化物半导体数字的四重2输入排外硅单片电.pdf（22页珍藏版）》请在麦多课文档分享上搜索。

1、LTR A B I Changes in accordance with NOR 5962-R162-98 98-09-02 Monica L. Poelking I DESCRIPTION DATE (YR-MO-DA) APPROVED 97-1 0-22 Monica L. Poelking Changes in accordance with NOR 5962-R313-97 C REV STATUS OF SHEETS Update boilerplate to MIL-PRF-38535 and updated appendix A. Editorial changes throu

2、ghout. - tmh 00-08-1 O Monica L. Poelking R EV SHEET PMIC NIA cccccccccccccc 12 3 4 5 6 7 8 9 1011 1213 14 PREPAREDBY Thanh V. Nguyen STANDARD I CHECKEDBY I MICROCIRCUIT DRAW1 NG REVISION LEVEL C Thanh V. Nguyen SIZE CAGE CODE A 67268 5962-95660 THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS A

3、ND AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC NIA DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216 APPROVED BY Monica L. Poelking DRAWING APPROVAL DATE 95-1 2-29 MICROCIRCUIT, DIGITAL, RADIATION EXCLUSIVE OR GATE, TTL COMPATIBLE INPUTS, MONOLITHIC SILICON HARDENED, ADVANCED CMOS, QUAD 2-INPUT I I

4、 I I SHEET 1 OF 21 DSCC FORM 2233 APR 97 DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited. 5962-E380-00 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-1. SCOPE DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 4321 6-5000

5、 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a

6、 choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. SIZE A REVISION LEVEL SHEET C 2 1.2 m. The PIN is as shown in the following example: 95660 Federal RHA Device Device Case Lead stock class designator type class outline finish designator (see 1.2.1) (see 1.2.2) designator

7、 (see 1.2.4) (see 1.2.5) I (see 1.2.3) V Drawing number 1.2.1 RHA desimator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA le

8、vels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device tvpefs). The device type(s) identify the circuit function as follows: Device tvpe Generic number Circuit function o1 02 ACTS86 ACTS86-02 11 Radiation hardened SOS, advanced CMOS, quad 2-input

9、 exclusive OR gate, lTL compatible inputs Radiation hardened SOS, advanced CMOS, quad 2-input exclusive OR gate, lTL compatible inputs 1.2.3 Device class desimator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements doc

10、umentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q orV Certification and qualification to MIL-PRF-38535 1.2.4 Case outlinefs). The case outline(s) are as designated in MIL-STD-1835 a

11、nd as follows: Outline letter Descriptive desimator Terminals Packacie stvle C X CDIP2-Tl4 14 CDFP3-F14 14 dual-in-line package f I at package 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. - 11 Device t

12、ype -02 is the same as device type -01 except that the device type -02 products are manufactured at an overseas wafer foundry. Device type -02 is used to positively identify, by marketing part number and by brand of the actual device, material that is supplied by an overseas foundry. I 5962-95660 ST

13、ANDARD MICROCIRCUIT DRAWING DSCC FORM 2234 APR 97 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-1.3 Absolute maximum ratinas. 1/ 21 31 Supply voltage range (VCC) . -0.5 V dc to +7.0 V dc DC input voltage range (VIN) . -0.5 V dc to VCC + 0.5 V dc DC

14、 input current, any one input DC output current, any one output (IOUT) and the absolute value of the magnitude, not the sign, is relative to the minimum and maximum limits, as applicable, listed herein. Devices supplied to this drawing meet all levels M, D, L, R, and F of irradiation. However, this

15、device is only tested at the “F“ level. Pre and post irradiation values are identical unless otherwise specified in table I. When performing post irradiation electrical measurements for any RHA level, TA = +25“C. ForceIMeasure functions may be interchanged. This test may be performed either one inpu

16、t at a time (preferred method) or with all input pins simultaneously at VIN = VCC - 2.1 V (alternate method). Classes Q and V shall use the preferred method. When the test is performed using the alternate test method, the maximum limit is equal to the number of inputs at a high TL input level times

17、1 .O mA; and the preferred method and limits are guaranteed. For the preferred method, a minimum of one input shall be tested. All other inputs shall be guaranteed, if not tested, to the limits specified in table I herein. Power dissipation capacitance (CPD) determines both the power consumption (PD

18、) and current consumption (IS). Where PD = (CPD + CL) (Vcc x Vcc)f + (lcc x Vcc) + (n x d x Alcc x Vcc) IS = (CPD + CL) Vccf + ICC + (n x d x Alcc) f is the frequency of the input signal; n is the number of device inputs at TL levels; and d is the duty cycle of the input signal. The test vectors use

19、d to verify the truth table shall, at a minimum, test all functions of each input and output. All possible input to output logic patterns per function shall be guaranteed, if not tested, to the truth table in figure 2 herein. For VOUT measurements, L 5 0.5 V and H 2 4.0 V. AC limits at VCC = 5.5 V a

20、re equal to the limits at VCC = 4.5 V. For propagation delay tests, all paths must be tested. STANDARD MICROCIRCUIT DRAWING IA SIZE I I 5962-95660 DSCC FORM 2234 APR 97 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-Device type Case outlines Termina

21、l number 1 2 3 4 5 6 7 Terminal number 8 9 10 11 12 13 14 All Terminal symbol Y3 A3 B3 Y4 A4 B4 vcc Terminal symbol DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 4321 6-5000 Al B1 Y1 A2 B2 Y2 GND SIZE A REVISION LEVEL SHEET C 9 C and X I FIGURE 1. Terminal connections. H = High voltage level L = Low

22、 voltage level FIGURE 2. Truth table. An Bn -)D- n FIGURE 3. Loqic diaqram. I 5962-95660 STANDARD MICROCIRCUIT DRAWING DSCC FORM 2234 APR 97 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-I- DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 4321 6-5000

23、INPUT SIZE A REVISION LEVEL SHEET C 10 3.0 V 2.7 V 1.3 V 0.3 V 0.0 v OH 80% 1.3 V 20% VOL POINT DuTcT TEST NOTES: 1. 2. 3. CL = 50 pF minimum or equivalent (includes test jig and probe capacitance). RL = 500Q or equivalent. Input signal from pulse generator: VIN = 0.0 V to 3.0 V; PRR 5 10 MHz; t, 5

24、3.0 ns; tf 5 3.0 ns; t, and tf shall be measured from 0.3 V to 2.7 V and from 2.7 V to 0.3 V, respectively. FIGURE 4. Switchinq waveforms and test circuit. I 5962-95660 STANDARD MICROCIRCUIT DRAWING DSCC FORM 2234 APR 97 Provided by IHSNot for ResaleNo reproduction or networking permitted without li

25、cense from IHS-,-,-4.4 Conformance inspection. Technology conformance inspection for classes Q and V shall be in accordance with MIL-PRF-38535 including groups A, B, C, D, and E inspections and as specified herein except where option 2 of MIL-PRF-38535 permits alternate in-line control testing. Qual

26、ity conformance inspection for device class M shall be in accordance with MIL-PRF-38535, appendix A and as specified herein. Inspections to be performed for device class M shall be those specified in method 5005 of MIL-STD-883 and herein for groups A, B, C, D, and E inspections (see 4.4.1 through 4.

27、4.4). 4.4.1 Group A inspection. Subgroups (in accordance with MIL-STD-883, method 5005, table I) Device class M 1,7,9 a. Tests shall be as specified in table IIA herein. Subgroups (in accordance with MIL-PRF-38535, table Ill) Device Device class Q class V 1,7,9 1,7,9 b. For device class M, subgroups

28、 7 and 8 tests shall be sufficient to verify the truth table. For device classes Q and V, subgroups 7 and 8 shall include verifying the functionality of the device; these tests shall have been fault graded in accordance with MIL-STD-883, test method 5012 (see 1.5 herein). Subgroup 4, 5 and 6 (CIN an

29、d CPD measurement) shall be measured only for the initial qualification and after process or design changes which may affect capacitance. CIN shall be measured between the designated terminal and GND at a frequency of 1 MHz. For CIN and CPD the tests shall be sufficient to validate the limits define

30、d in table I herein. c. Final electrical parameters (see 4.2) Group A test requirements (see 4.4) Group C end-point electrical Group D end-point electrical Group E end-point electrical parameters (see 4.4) parameters (see 4.4) parameters (see 4.4) TABLE IIA. Electrical test requirements. 1,2,3,7,8,9

31、,10,11 1,2,3,7,8,9, 1,2,3,7,8,9, - 11 10,ll 11 10, 11 2/31 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 9, 10, 11 7,8,9,10,11 7,8,9,10,11 1, 2, 3, 7, 8, 9, 10, 11 1, 2, 3, 7, 8, 9, 1, 2, 3, 4, 5, 6, 1, 2, 3, 7, 8, 9, 10,ll 10,ll 31 1,7,9 1,7,9 1,7,9 1,7,9 1,7,9 1,7,9 Test requirements DEFENSE SUPPLY CE

32、NTER COLUMBUS COLUMBUS, OHIO 4321 6-5000 Interim electrical parameters (see 4.2) REVISION LEVEL SHEET C 11 I Parameters 11 I Delta limits I I ICC I 11 .O pA I I I1 5% I lOL/lOH I - 11 These parameters shall be recorded before and after the required burn-in and life test to determine delta limits. 4.

33、4.2 Group C inspection. The group C inspection end-point electrical parameters shall be as specified in table II herein. STANDARD MICROCIRCUIT DRAWING IA SIZE I I 5962-95660 DSCC FORM 2234 APR 97 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-4.4.2.

34、1 Additional criteria for device class M. Steady-state life test conditions, method 1005 of MIL-STD-883: a. Test condition A, B, C or D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity u

35、pon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1005 Of MIL-STD-883. DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 4321 6-5000 b. TA = +125“C, minimum. SIZE A REVISION LEVEL SHEET C

36、12 c. Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883. 4.4.2.2 Additional criteria for device classes Q and V. The steady-state life test duration, test condition and test temperature, or approved alternatives shall be as specified in the device manufacturers QM plan in

37、 accordance with MIL-PRF-38535. The test circuit shall be maintained under document revision level control by the device manufacturers TRB in accordance with MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the inputs, outp

38、uts, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1005 of MIL-STD-883. 4.4.3 Group D inspection. The group D inspection end-point electrical parameters shall be as specified in table II herein. 4.4.4 Group E inspection. Group E inspection is re

39、quired only for parts intended to be marked as radiation hardness assured (see 3.5 herein). RHA levels for device classes M, Q and V shall be as specified in MIL-PRF-38535. End-point electrical parameters shall be as specified in table IIA herein. 4.4.4.1 Total dose irradiation testing. Total dose i

40、rradiation testing shall be performed in accordance with MIL-STD-883 method 1 O1 9 and as specified herein. 4.4.4.1.1 Accelerated aqinq test. Accelerated aging tests shall be performed on all devices requiring a RHA level greater than 5k rads(Si). The post-anneal end-point electrical parameter limit

41、s shall be as specified in table I herein and shall be the pre-irradiation end-point electrical parameter limit at +25“C 15“c. Testing shall be performed at initial qualification and after any design or process changes which may affect the RHA response of the device. 4.4.4.2 Dose rate induced latchu

42、p testing. Dose rate induced latchup testing shall be performed in accordance with test method 1020 of MIL-STD-883 and as specified herein (see 1.4 herein). Tests shall be performed on devices, SEC, or approved test structures at technology qualification and after any design or process changes which

43、 may effect the RHA capability of the process. 4.4.4.3 Dose rate upset testing. Dose rate upset testing shall be performed in accordance with test method 1021 of MIL- STD-883 and herein (see 1.4 herein). a. Transient dose rate upset testing shall be performed at initial qualification and after any d

44、esign or process changes which may effect the RHA performance of the devices. Test 1 O devices with O defects unless otherwise specified. b. Transient dose rate upset testing for class Q and V devices shall be performed as specified by a TRB approved radiation hardness assurance plan and MIL-PRF-385

45、35. 4.4.4.4 Sinde event phenomena SEP). SEP testing shall be required on class V devices (see 1.4 herein). SEP testing shall be performed on a technology process on the Standard Evaluation Circuit (SEC) or alternate SEP test vehicle as approved by the qualifying activity at initial qualification and

46、 after any design or process changes which may affect the upset or latchup characteristics. The recommended test conditions for SEP are as follows: a. The ion beam angle of incidence shall be between normal to the die surface and 60“ to the normal, inclusive (.e. O“ a b. The fluence shall be t 1 O0

47、errors or t 1 O6 ions/cm2. c. The flux shall be between 10 and 1 O5 ions/cm2/s. The cross-section shall be verified to be flux independent by angle a 60“). No shadowing of the ion beam due to fixturing or package related effects is allowed. measuring the cross-section at two flux rates which differ

48、by at least an order of magnitude. d. The particle range shall be t 20 microns in silicon. e. The test temperature shall be +25“C and the maximum rated operating temperature 11 0C. I 5962-95660 STANDARD MICROCIRCUIT DRAWING DSCC FORM 2234 APR 97 Provided by IHSNot for ResaleNo reproduction or networ

49、king permitted without license from IHS-,-,-f. Bias conditions shall be defined by the manufacturer for latchup measurements. g. Test four devices with zero failures. 4.5 Methods of inspection. Methods of inspection shall be as specified as follows: 4.5.1 Voltaqe and current. Unless otherwise specified, all voltages given are referenced to the microcircuit GND terminal. Currents given are conventional current and positive when flowing int