DLA SMD-5962-92228-1994 MICROCIRCUIT DIGITAL FAST CMOS 10-BIT BUS INTERFACE LATCH WITH NONINVERTING THREE-STATE OUTPUTS TTL COMPATIBLE INPUTS AND LIMITED OUTPUT VOLTAGE SWING MONOL.pdf
《DLA SMD-5962-92228-1994 MICROCIRCUIT DIGITAL FAST CMOS 10-BIT BUS INTERFACE LATCH WITH NONINVERTING THREE-STATE OUTPUTS TTL COMPATIBLE INPUTS AND LIMITED OUTPUT VOLTAGE SWING MONOL.pdf》由会员分享,可在线阅读,更多相关《DLA SMD-5962-92228-1994 MICROCIRCUIT DIGITAL FAST CMOS 10-BIT BUS INTERFACE LATCH WITH NONINVERTING THREE-STATE OUTPUTS TTL COMPATIBLE INPUTS AND LIMITED OUTPUT VOLTAGE SWING MONOL.pdf(21页珍藏版)》请在麦多课文档分享上搜索。
1、1 SUD-5762-92228 = 9799996 0064503 T1 .-IIu-I DRAWING APPROVAL DATE 94-1 0-1 8 REVISION LEVEL PREPARED BY PMIC NIA Joseph A. Kerby I DEFENSE ELECTRONICS SUPPLY CENTER OUTPUT VOLTAGE SWING, MONOLITHIC SILICON SIZE CAGE CODE 5962-92228 A 67268 SHEET 1 OF 20 DAYTON, OHIO 45444 CHECKED BY STANDARD MICRO
2、CIRCUIT Thanh V. Nguyen DRAWING MICROCIRCUIT, DIGITAL, FAST CMOS, . 10-BIT BUS INTERFACE LATCH WITH THIS DRAWING IS AVAIUBLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC N/A I NONINVERTING THREE-STATE OUTPUTS, I TTL COMPATIBLE INPUTS AND LIMITED APPROVED BY Monica L. Poe
3、lking I kSC bORH 1Y5 JUL 94 DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited. 59624358-94 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SND-59b2-92228 999999b 00b4504 953 SIZE STANDARD A MICROCIRCUIT DRAWING DEFENSE
4、ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 REVISION LEVEL 1. SCOPE 1.1 Sfope. This drawing forms a part of a OM part - one part number documentation system (see 6.6 herein). Two product assurance classes umsisting of military high reliability (device classes Q and n) and spce application (device c
5、lass V), and a choice of case wtlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). 1.2.1 of NIL-STD-883, “Provisions for the use of RIL-STD-883 in conjunction with coqliant non-JAN devices“. available, a choice of Radiation Hardness Assurance CRHA) level
6、s are reflected in the PIN. Dcvice class n microcircuits represent non-JAN class microcircuits in accordance with Uhen 1.2 m. The PIN shall be as shown in the following exailple: sw2 - 92228 - o1 N K X I I I I I I I I I I I I - Lead case Device Devi ce RHA Federal stock class designator type class o
7、utline finish designator (See 1.2.1) (See 1.2.2) designator (See 7.2.4) (See 1.2.5) / (See 1.2.3) / Drawing number 1.2.7 RHA desiqnator. Device class N RHA marked devices shall meet the MIL-1-38535 appendix A specified RHA Levels and shall be Mrked with the appropriate AHA designator. NIL-1-38535 Sp
8、ecified RHA levels and shall be marked with the appropriate RHA designator. non-RHA device. Device classes Q and V MA marked devices shall meet the A dash (-) indicates a 5962-92228 SHEET 2 1.2.2 Device typeW. The device type(s) shall identify the circuit function as follows: Devi ce tyM Generic num
9、ber Circuit function 01 54FCT841AT 1Pbit bus interface latch with minverting three-stete outputs, TTL compatible inputs and linited output voltage swing. 10-bit bus interface latch with noninverting three-state outputs, TTL compatible inputs and Limited output voltage swing. 10-bit bus interface lat
10、ch with noninverting three-state outputs, TTL compatible inputs and limited output voltage suing. 02 54FCT841BT 03 54FCT841CT 1.2.3 Device class desianator. The device class designator shall be a single letter identifying the product assurance level as follows: Device class Device requirements docum
11、entation Vendor sclf-certification to the requirements for non-JAN class B microcircuits in accordance with 1.2.1 of RIL-STD-883 Q or V Certification and qualification to MIL-1-38535 1.2.4 Case outline(s). The case outline(s1 shall be as designated in RIL-STD-1835, and as follows: utline letter Desc
12、riptive designator Terni nals Package style K L 3 GDFP2-F24 or CDFP3-F24 24 Flat package GDIP3-T24 or CDIP4-T24 24 Dual-in-line package CQCCI-NZ8 28 Lcadless-chip-carrier package 1.2.5 Lead finish. lhe lead finish shall be as specified in NIL-STD-883 (see 3.1 herein) for class ki or MIL-1-38535 for
13、classes Q and V. designation is for use in specifications when lead finishes A, B, and c are cansidered acceptable and interchangeable without preference. Finish letter “X“ shall not be mrked on the microcircuit or its packaging. The “X“ Provided by IHSNot for ResaleNo reproduction or networking per
14、mitted without license from IHS-,-,-1.3 Absolute maximum ratinqs. 11 g/ I/ Supply voltage range (V - - - - - - - - - - - - - - - - - Dc input voltage range LIN) - - - - - - - - - - - - - - - - OC output voltage range (V 1 - - - - - - - - - - - - - - - DC input clamp current (I y(VIN = -0.5 V) - - -
15、- - - - - - DC output clamp current (i, (VouT = -0.5 V and +7.0 V) - - DC output source current (I ) per output - - - - - - - - - - DC output sink current (IOLyper output - - - - - - - - - - - DC ground currentCFtND) - - - - - - - - - - - - - - - - - - Storage temperature range (T 1 - - - - - - - -
16、- - - - - - Case temperature under bias !?T:IAs) - - - - - - - - - - - - - Haxiwm power dissipation (PD) - - - - - - - - - - - - - - - Lead temperature (soldering, 10 seconds) - - - - - - - - - - Thermal resistance, junction-to-case (eJc) - - - - - - - - - Junction terperature (TJ) - - - - - - - - -
17、 - - -_- - - - - - 1.4 Recommended weratinq conditions. g/ s/ Supply voltage range (Vc - - - - - - - - - - - - - - - - - input voltage range (v 3 - - - - - - - - - - - - - - - - - - output voltage range td,) - - - - - - - - - - - - - - - - - Maximum low level input voltage (VIL) - - - - - - - - - -
18、- - niniaun high level input voltage (VI 1 - - - - - - - - - - - Case operating temperature range (T !i - - - - - - - - - - - - Maximum input rise and fall rate (kt1AV): (from VIN 0.3 V to 2.7 V, 2.7 v to 0.3 V) - - - - - - - - Maximum high level output current (I ) - - - - - - - - - - - mximum tow
19、levei output current CI:! - - - - - - - - - - - DC Vcc current (I ) - - - - - - - - - - - - - - SIZE STANDARD A MICROCIRCUIT DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 REVISION LEVEL 1.5 Digital logic testing for device classes Q and V. 5962-92228 SHEET 3 Fault coverage measurement
20、 of manufacturing logic tests (MIL-STD-883, test method 5012) - - - - - - - - -0.5 V dc to t7.0 V dc -0.5 V dc to Vcc t 0.5 V dc -0.5 V dc to Vcc + 0.5 V dc -20 mA I20 IRA -30 niA +70 mA I260 InA i550 mA -65C to +15OoC -65OC to +13SoC 500 mu +3woc See HI L- STD-I 835 +175“C I_/ 41 t4.5 V dc to +5.5
21、V dc tO.0 V dc to Vcc t0.0 V dc to Vcc 0.8 V 2.0 v -55C to t125“C 5 ns1V -12 niA 32 RA XX percent 51 - 11 Stresses above the absolute maximum rating may cause permanent damage to the device. maximum levels may degrade performance and affect reliability. Unless otherwise noted, all voltages are refer
22、enced to GND. The limits for the parameters specified herein shall apply over the full specified Vcc range and case temperature range of -55C to +125C. $1 For Vcc 2 6.5 V, the upper limit on the range is limited to 7.0 V. - 51 Values will be added when they become available. Extended operation at th
23、e - 21 - 31 DESC FORM 193A JUL 94 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-59b2-92228 999999b 00b450b 72b 2. APPLICABLE DOCWENTS 2.1 Government wecification, standards, bulletin, and handbook. Unless otherwise specified, the follouing spec
24、ification, standards, bulletin, and handbook of the issue listed in that issue of the Department of Defense Index of Specifications and Standards specified in the solicitation, form a part of this drawing to the extent specified here in . SPECIFICATION MILITARY HIL-1-38535 - STANDARDS MILITARY HIL-S
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