DLA SMD-5962-89701 REV C-2013 MICROCIRCUIT DIGITAL HIGH-SPEED CMOS QUAD D-TYPE FLIP-FLOP WITH RESET TTL COMPATIBLE INPUTS MONOLITHIC SILICON.pdf

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1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Changes in accordance with NOR 5962-R328-92. - JAK 92-09-25 Monica L. Poelking B Add notes to figure 4, switching waveforms and test circuit. Update boilerplate to MIL-PRF-38535 requirements. Editorial changes throughout. LTG 06-11-07 Thomas M. H

2、ess C Update boilerplate paragraphs to the current MIL-PRF-38535 requirements. - LTG 13-02-21 Thomas M. Hess REV SHEET REV SHEET REV STATUS REV C C C C C C C C C C OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 PMIC N/A PREPARED BY Marcia B. Kelleher DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.l

3、andandmaritime.dla.mil STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC N/A CHECKED BY Ray Monnin APPROVED BY Michael A. Frye MICROCIRCUIT, DIGITAL, HIGH-SPEED CMOS, QUAD D-TYPE FLIP-FLOP WITH RESET, TTL COMPATIBLE INPU

4、TS, MONOLITHIC SILICON DRAWING APPROVAL DATE 89-07-24 REVISION LEVEL C SIZE A CAGE CODE 67268 5962-89701 SHEET 1 OF 10 DSCC FORM 2233 APR 97 5962-E248-13 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89701

5、DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (P

6、IN). The complete PIN is as shown in the following example: 5962-89701 01 E A Drawing number Device type (see 1.2.1) Case outline (see 1.2.2) Lead finish (see 1.2.3) 1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 54HC

7、T175 Quad D-type flip-flop with reset, TTL compatible inputs 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style E GDIP1-T16 or CDIP2-T16 16 Dual-in-line 1.2.3 Lead finish. The lead finish is as sp

8、ecified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. 1/ 2/ 3/ Supply voltage range (VCC) -0.5 V dc to +7.0 V dc DC input voltage range (VIN) -0.5 V dc to VCC+ 0.5 V dc DC output voltage range (VOUT) . -0.5 V dc to VCC+ 0.5 V dc Clamp diode current (IIK, IOK) 20 mA DC output current (p

9、er pin) 20 mA DC drain current (per pin) 25 mA DC VCCor GND current 50 mA Storage temperature range (TSTG) -65C to +150C Maximum power dissipation (PD) . 500 mW 4/ Lead temperature (soldering, 10 seconds) . +300C Thermal resistance, junction-to-case (JC) . See MIL-STD-1835 Junction temperature (TJ)

10、. +175C _ 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2/ Unless otherwise specified, all voltages are referenced to ground. 3/ The limits for the parameters specified

11、herein shall apply over the full specified VCCrange and case temperature range of -55C to +125C. 4/ For TC= +100C to +125C, derate linearly at 8 mW/C. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89701 DLA

12、 LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 3 DSCC FORM 2234 APR 97 1.4 Recommended operating conditions. Supply voltage range (VCC) +4.5 V dc to +5.5 V dc Case operating temperature range (TC) . -55C to +125C Input rise or fall time (tr, tf): VCC= 4.5 V . 0 to 500 ns Minimum

13、 setup time, data to CP (ts): TC= 25C, VCC= 4.5 V . 20 ns TC= -55C to +125C, VCC= 4.5 V . 30 ns Minimum hold time, data to CP (th): TC= 25C, VCC= 4.5 V . 5 ns TC= -55C to +125C, VCC= 4.5 V . 5 ns Minimum removal time, MR to CP (trem): TC= 25C, VCC= 4.5 V . 5 ns TC= -55C to +125C, VCC= 4.5 V . 5 ns M

14、inimum MR pulse width (tw): TC= 25C, VCC= 4.5 V . 20 ns TC= -55C to +125C, VCC= 4.5 V . 30 ns Minimum clock pulse width (tw): TC= 25C, VCC= 4.5 V . 20 ns TC= -55C to +125C, VCC= 4.5 V . 30 ns Maximum clock frequency (fMAX): TC= 25C, VCC= 4.5 V . 25 MHz TC= -55C to +125C, VCC= 4.5 V . 16 MHz 2. APPLI

15、CABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTM

16、ENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK

17、-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094). 2.2 Non-

18、Government publications. The following document(s) form a part of this document to the extent specified herein. Unless otherwise specified, the issues of these documents cited in the solicitation or contract. JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JESD7 - Standard for Description of 54/74H

19、CXXXXX and 54/74HCTXXXXX Advanced High-Speed CMOS Devices. (Copies of these documents are available online at http:/www.jedec.org or from JEDEC Solid State Technology Association, 3103 North 10thStreet, Suite 240-S Arlington, VA 22201-2107). Provided by IHSNot for ResaleNo reproduction or networking

20、 permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89701 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 4 DSCC FORM 2234 APR 97 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein,

21、 the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for n

22、on-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in ac

23、cordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of t

24、he device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensio

25、ns shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table. The truth table shall be as specified on figur

26、e 2. 3.2.4 Logic diagram. The logic diagram shall be as specified on figure 3. 3.2.5 Switching waveforms and test circuit. The switching waveforms and test circuit shall be as specified on figure 4. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical perform

27、ance characteristics are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marki

28、ng. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has

29、 the option of not marking the “5962-“ on the device. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in acco

30、rdance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to

31、DLA Land and Maritime -VA prior to listing as an approved source of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix

32、A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DLA Land and Maritime -VA shall be required for any change that affects this drawing. 3.9 Verification and review. DLA Land and Maritime, DLA Land and Maritimes agent,

33、and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS

34、-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89701 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Test conditions 1/ -55C TC +125C unless otherwise specified Group A subgroups Device type L

35、imits Unit Min Max High level output voltage VOHVCC= 4.5 V VIN= 2.0 V or 0.8 V IOH= -20 A 1, 2, 3 01 4.4 V IOH= -4.0 mA 3.7 Low level output voltage VOLVCC= 4.5 V VIN= 2.0 V or 0.8 V IOL= +20 A 1, 2, 3 01 0.1 V IOL= +4.0 mA 0.4 High level input voltage 2/ VIHVCC= 4.5 V 1, 2, 3 01 2.0 V Low level inp

36、ut voltage 2/ VILVCC= 4.5 V 1, 2, 3 01 0.8 V Input capacitance CINVIN= 0 V, TC= +25C See 4.3.1c 4 01 10 pF Quiescent supply current ICCVCC= 5.5 V, IOUT= 0.0 A VIN= VCCor GND 1, 2, 3 01 160 A Input leakage current IINVCC= 5.5 V VIN= VCCor GND 1, 2, 3 01 1.0 A Additional quiescent supply current 3/ IC

37、CAny 1 input VIN = 2.4 V Other inputs: VIN= VCCor GND IOUT= 0.0 A VCC= 5.5 V 1, 2, 3 01 1.8 mA Functional tests See 4.3.1d 7, 8 01 Propagation delay time, CP to Qn or Qn tPHL1, tPLH1VCC= 5.0 V 10% CL= 50 pF 10% See figure 4 9 01 33 ns 10, 11 50 Propagation delay time, MR to Qn or Qn tPHL2, tPLH29 01

38、 40 ns 10, 11 60 Transition time 3/ tTLH, tTHL9 01 15 ns 10, 11 22 1/ For a power supply of 5 V 10 percent, the worst case output voltages (VOHand VOL) occur for HCT at 4.5 V. Thus, the 4.5 V values should be used when designing with this supply. Worst cases VIHand VILoccur at VCC= 5.5 V and 4.5 V,

39、respectively. 2/ VIHand VILtests are not required and shall be applied as forcing functions for VOHand VOLtests. 3/ Guaranteed, if not tested, to the specified limits in table I. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT D

40、RAWING SIZE A 5962-89701 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 6 DSCC FORM 2234 APR 97 Device type 01 Case outline E Terminal number Terminal symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 MR Q0 Q0 D0 D1 Q1 Q1 GND CP Q2 Q2 D2 D3 Q3 Q3 VCCFIGURE 1. Terminal connections

41、. Inputs Outputs MR CP Dn Qn Qn L X X L H H H H L H L L H H L X Q0 Q0 H = High voltage level L = Low voltage level X = Irrelevant = Transition from low-to-high Q0, Q0 = Levels before the indicated steady-state input conditions were established FIGURE 2. Truth table. Provided by IHSNot for ResaleNo r

42、eproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89701 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 7 DSCC FORM 2234 APR 97 FIGURE 3. Logic diagram. Provided by IHSNot for ResaleNo reproduction or networking permitte

43、d without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89701 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 8 DSCC FORM 2234 APR 97 NOTES: 1. Includes test jig and probe capacitance. 2. Input signal from pulse generator: VIN = 0.0 V to VCC; PRR 1 MHz; ZO = 5

44、0; tr = 6.0 ns; tf = 6.0 ns; tr and tf shall be measured from 0.1 VCCto 0.9 VCCand from 0.9 VCCto 0.1 VCC, respectively; duty cycle = 50 percent. 3. The outputs are measured one at a time with one transition per measurement. FIGURE 4. Switching waveforms and test circuit. Provided by IHSNot for Resa

45、leNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89701 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 9 DSCC FORM 2234 APR 97 4. VERIFICATION 4.1 Sampling and inspection. Sampling and inspection procedures shall

46、be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening. Screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection. The following additional criteria shall apply: a. Burn-in test, method 1015 of MIL-STD-883.

47、 (1) Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as app

48、licable, in accordance with the intent specified in method 1015 of MIL-STD-883. (2) TA= +125C, minimum. b. Interim and final electrical test parameters shall be as specified in table II herein, except interim electrical parameter tests prior to burn-in are optional at the discretion of the manufacturer. TABLE II. Electrical test requirements. MIL-STD-883 test requirements Subgroups (in accordance with MIL-STD-883, method 5005, table I) Interim electrical parameters (method 5004) - Final