DLA SMD-5962-84088 REV E-2009 MICROCIRCUIT DIGITAL HIGH-SPEED CMOS DUAL J-K FLIP-FLOP WITH SET AND RESET MONOLITHIC SILICON.pdf

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1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED B Convert to Military Drawing Format. Add vendor CAGE 18714 for device type 01. Editorial changes throughout. 86-12-01 N. A. Hauck C Add vendor CAGE 27014 to case outline “F” and case outline “2”. Inactivate device 01 case outline “E” for new desig

2、n. Change drawing CAGE to 67268. 87-08-27 N. A. Hauck D Update boilerplate to MIL-PRF-38535 requirements. - CFS 01-12-11 Thomas M. Hess E Update the boilerplate paragraphs to current requirements as specified in MIL-PRF-38535. - jak 09-07-09 Thomas M. Hess The original first sheet of this drawing ha

3、s been replaced. REV SHET REV SHET REV STATUS REV E E E E E E E E E E E E E OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 PMIC N/A PREPARED BY Marvin Carey DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil STANDARD MICROCIRCUIT DRAWING CHECKED BY D. A. DiCenzo THIS DRAW

4、ING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY N. A. Hauck MICROCIRCUIT, DIGITAL, HIGH-SPEED CMOS, DUAL J-K FLIP-FLOP WITH SET AND RESET, MONOLITHIC SILICON AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 84-10-05 AMSC N/A REVISION LEVEL E SIZE A CAGE CODE 67268 84088 SHEET

5、1 OF 13 DSCC FORM 2233 APR 97 5962-E329-09 .Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 84088 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.

6、1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 84088 01 E A Drawing number Device type (see 1

7、.2.1) Case outline(see 1.2.2) Lead finish(see 1.2.3)1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 54HC112 Dual J-K flip-flop with set and reset 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-

8、1835 and as follows: Outline letter Descriptive designator Terminals Package style E GDIP1-T16 or CDIP2-T16 16 Dual-in-line F GDFP2-F16 or CDFP3-F16 16 Flat pack 2 CQCC1-N20 20 Square leadless chip carrier 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute

9、maximum ratings. 1/ 2/ 3/ Supply voltage range (VCC) . -0.5 V dc to +7.0 V dc DC input voltage range (VIN) . -0.5 V dc to VCC+ 0.5 V dc DC output voltage range (VOUT) -0.5 V dc to VCC+ 0.5 V dc Clamp diode current 20 mA DC output current (per pin) . 25 mA DC VCCor GND current (per pin) 50 mA Storage

10、 temperature range (TSTG) -65C to +150C Maximum power dissipation (PD) 500 mW 4/ Lead temperature (soldering, 10 seconds) +260C Thermal resistance, junction-to-case (JC) See MIL-STD-1835 Junction temperature (TJ) . +175C 1.4 Recommended operating conditions. 2/ 3/ Supply voltage range (VCC) . +2.0 V

11、 dc to +6.0 V dc Input voltage range (VIN) . 0.0 V to VCCOutput voltage range (VOUT) 0.0 V to VCCCase operating temperature range (TC) -55C to +125C _ 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performa

12、nce and affect reliability. 2/ Unless otherwise specified, all voltages are referenced to ground. 3/ The limits for the parameters specified herein shall apply over the full specified VCCrange and case temperature range of -55C to +125C. 4/ For TC= +100C to + 125C, derate linearly at 12 mW/C. Provid

13、ed by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 84088 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 3 DSCC FORM 2234 APR 97 1.4 Recommended operating conditions - Continued. Maximum inp

14、ut rise and fall time (tr, tf): TC= +25C VCC= 2.0 V dc 1000 ns VCC= 4.5 V dc 500 ns VCC= 6.0 V dc 400 ns TC= -55C, +125C VCC= 2.0 V dc 1000 ns VCC= 4.5 V dc 500 ns VCC= 6.0 V dc 400 ns Minimum recovery time, set or reset to clock (tREC): TC= +25C VCC= 2.0 V dc 100 ns VCC= 4.5 V dc 20 ns VCC= 6.0 V d

15、c 17 ns TC= -55C, +125C VCC= 2.0 V dc 150 ns VCC= 4.5 V dc 30 ns VCC= 6.0 V dc 26 ns Minimum setup time, J or K to clock (ts): TC= +25C VCC= 2.0 V dc 100 ns VCC= 4.5 V dc 20 ns VCC= 6.0 V dc 17 ns TC= -55C, +125C VCC= 2.0 V dc 150 ns VCC= 4.5 V dc 30 ns VCC= 6.0 V dc 26 ns Minimum pulse width, set,

16、reset, or clock (tw): TC= +25C VCC= 2.0 V dc 100 ns VCC= 4.5 V dc 20 ns VCC= 6.0 V dc 17 ns TC= -55C, +125C VCC= 2.0 V dc 150 ns VCC= 4.5 V dc 30 ns VCC= 6.0 V dc 26 ns Minimum hold time, J or K from clock (th): TC= +25C VCC= 2.0 V dc 25 ns VCC= 4.5 V dc 5 ns VCC= 6.0 V dc 5 ns TC= -55C, +125C VCC=

17、2.0 V dc 40 ns VCC= 4.5 V dc 8 ns VCC= 6.0 V dc 7 ns Maximum clock frequency (fCL): TC= +25C VCC= 2.0 V dc 5 MHz VCC= 4.5 V dc 25 MHz VCC= 6.0 V dc 29 MHz TC= -55C, +125C VCC= 2.0 V dc 3 MHz VCC= 4.5 V dc 17 MHz VCC= 6.0 V dc 20 MHz Provided by IHSNot for ResaleNo reproduction or networking permitte

18、d without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 84088 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 4 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, an

19、d handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits Manufacturing, General Specification for. DEPARTM

20、ENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these docu

21、ments are available online at http:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, t

22、he text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non

23、-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in acco

24、rdance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the

25、 device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions

26、 shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table. The truth table shall be as specified on fig

27、ure 2. 3.2.4 Logic diagram. The logic diagram shall be as specified on figure 3. 3.2.5 Switching waveforms and test circuit. The switching waveforms and test circuit shall be as specified on figure 4. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical perfo

28、rmance characteristics are as specified in table I and shall apply over the full case operating temperature range. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 84088 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHI

29、O 43218-3990 REVISION LEVEL E SHEET 5 DSCC FORM 2234 APR 97 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535

30、, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked . For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device

31、. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML f

32、low option is used. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 and QML-38535 (see 6.6 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approve

33、d source of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits deliv

34、ered to this drawing. 3.8 Notification of change. Notification of change to DSCC-VA shall be required for any change that affect this drawing. 3.9 Verification and review. DSCC, DSCCs agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required doc

35、umentation. Offshore documentation shall be made available onshore at the option of the reviewer. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 84088 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVI

36、SION LEVEL E SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions -55C TC+125C unless otherwise specified 1/ Group A subgroups Limits Unit Min MaxHigh level output voltage VOHVIN= VIHor VILVCC=2.0 V 1, 2, 3 1.9 V IOH= -20 A VCC=4.5 V 4.4 VCC=6.0 V 5.9

37、 VIN= VIHor VILIOH= -4.0 mA VCC=4.5 V 3.7 IN= VIHor VILIOH= -5.2 mA VCC=6.0 V 5.2 Low level output voltage VOLVIN= VIHor VIL IOL= +20 A VCC=2.0 V 1, 2, 3 0.1 V VCC=4.5 V 0.1 VCC=6.0 V 0.1 VIN= VIHor VILIOL= +4.0 mA VCC=4.5 V 0.4 IN= VIHor VILIOL= +5.2 mA VCC=6.0 V 0.4 High level input voltage VIHVCC

38、=2.0 V 1, 2, 3 1.5 V 2/ VCC=4.5 V 3.15 VCC=6.0 V 4.2 Low level input voltage VILVCC=2.0 V 1, 2, 3 0.3 V 2/ VCC=4.5 V 0.9 VCC=6.0 V 1.2 Input capacitance CINVIN= 0.0 V, TC= +25C See 4.3.1c 4 10 pF Quiescent supply current ICCVCC= 6.0 V VIN= VCCor GND 1, 2, 3 80 A Input leakage current IINVCC= 6.0 V V

39、IN= VCCor GND 1, 2, 3 1.0 A Functional tests See 4.3.1d 7 Propagation delay time, CLK to Q tPHL1, tPLH1TC= +25C CL= 50 pF VCC=2.0 V 9 175 ns or Q 3/ See figure 4 VCC=4.5 V 35 VCC=6.0 V 30 TC= -55C and +125C CL= 50 pF VCC=2.0 V 10, 11 265 ns See figure 4 VCC=4.5 V 53 VCC=6.0 V 45 See footnotes at end

40、 of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 84088 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characterist

41、ics - Continued. Test Symbol Conditions -55C TC+125C unless otherwise specified 1/ Group A subgroups Limits Unit Min Max Propagation delay time, RESET to Q tPHL2, tPLH2TC= +25C CL= 50 pF VCC=2.0 V 9 185 ns or Q 3/ See figure 4 VCC=4.5 V 37 VCC=6.0 V 31 TC= -55C and +125C CL= 50 pF VCC=2.0 V 10, 11 2

42、80 ns See figure 4 VCC=4.5 V 56 VCC=6.0 V 48 Propagation delay time, SET to Q tPHL3, tPLH3TC= +25C CL= 50 pF VCC=2.0 V 9 185 ns or Q 3/ See figure 4 VCC=4.5 V 37 VCC=6.0 V 31 TC= -55C and +125C CL= 50 pF VCC=2.0 V 10, 11 280 ns See figure 4 VCC=4.5 V 56 VCC=6.0 V 48 Transition time high-to-low, tTHL

43、, tTLHTC= +25C CL= 50 pF VCC=2.0 V 9 75 ns low-to-high 4/ See figure 4 VCC=4.5 V 15 VCC=6.0 V 13 TC= -55C and +125C CL= 50 pF VCC=2.0 V 10, 11 110 ns See figure 4 VCC=4.5 V 22 VCC=6.0 V 19 1/ For a power supply of 5 V 10% the worst case output voltages (VOHand VOL) occur for HC at 4.5 V. Thus, the 4

44、.5 V values should be used when designing with this supply. Worst case VIHand VILoccur at VCC= 5.5 V and 4.5 V respectively. (The VIHvalue at 5.5 V is 3.85 V.) The worst case leakage current (IIN, and ICC) occur for CMOS at the higher voltage, and so the 6.0 V values should be used. Power dissipatio

45、n capacitance (CPD), typically 80 pF, determines the no load dynamic power consumption, PD= CPDVCC2f + ICCVCC, and the no load dynamic current consumption, IS= CPDVCCf + ICC. 2/ VIHand VILtests are not required if applied as a forcing function for VOHand VOL. 3/ AC testing at VCC= 2.0 V and VCC= 6.0

46、 V shall be guaranteed, if not tested, to the limits specified in table I. 4/ Transition time (tTHL, tTLH), if not tested, shall be guaranteed to the specified parameters. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING

47、SIZE A 84088 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 8 DSCC FORM 2234 APR 97 Device type 01 Case outlines E and F 2 Terminal number Terminal symbol 1 CLK1 NC 2 K1 CLK1 3 J1 K1 4 SET1 J1 5 Q1 SET1 6 Q1 NC 7 Q2 Q1 8 GND Q1 9 Q2 Q2 10 SET2 GND 11 J2 NC 12 K2 Q2 1

48、3 CLK2 SET2 14 RESET2 J2 15 RESET1 K2 16 VCCNC 17 - CLK2 18 - RESET2 19 - RESET1 20 - VCCNC = No connection FIGURE 1. Terminal connections. (each flip-flop) Inputs Outputs SET RESET CLK J K Q _ Q L H L H H H H H H L L H H H H H X X X H X X X L H L H X X X X L L H H X H L L* Q0H L Toggle Q0L H L* Q0L H Toggle Q0H = High voltage level L = Low voltage level X = Irrelevant = High to low level transition Q0= The level of Q before the indicated input con