DLA SMD-5962-01518 REV D-2006 MICROCIRCUIT MEMORY DIGITAL CMOS FIELD PROGRAMMABLE GATE ARRAY 32 000 GATES MONOLITHIC SILICON《单片硅32 000门数字存储器微电路CMOS 现场可编程门阵列》.pdf

《DLA SMD-5962-01518 REV D-2006 MICROCIRCUIT MEMORY DIGITAL CMOS FIELD PROGRAMMABLE GATE ARRAY 32 000 GATES MONOLITHIC SILICON《单片硅32 000门数字存储器微电路CMOS 现场可编程门阵列》.pdf》由会员分享，可在线阅读，更多相关《DLA SMD-5962-01518 REV D-2006 MICROCIRCUIT MEMORY DIGITAL CMOS FIELD PROGRAMMABLE GATE ARRAY 32 000 GATES MONOLITHIC SILICON《单片硅32 000门数字存储器微电路CMOS 现场可编程门阵列》.pdf（22页珍藏版）》请在麦多课文档分享上搜索。

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Changed the table I limits for IIL/IIH and IOZ from 10 A min and 10 A max to 20 A min and 20 A max. ksr 02-11-22 Raymond Monnin B Changed the table I limits for VCCI= 3.3 V operation, for IIL/IIH from 10 A min and 10 A max to 20 A min and 20 A ma

2、x. ksr 02-12-20 Raymond Monnin C Updated paragraph 4.4.1f. ksr 03-03-25 Raymond Monnin D Added case outline Z. Changed JCin section 1.3 from 6.3 oC/W to 2.0 oC/W. Updated sections 3.2.3.1, 3.2.3.2, 3.11, 3.11.1, and 3.11.2 to remove Altered Item Drawing reference. ksr 06-10-30 Raymond Monnin REV SHE

3、T REV D D D D D D D SHEET 15 16 17 18 19 20 21 REV STATUS REV D D D D D D D D D D D D D D OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Kenneth Rice DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY Rajesh Pithadia COLUMBUS, OHIO 43218-3990 http:/www.dsc

4、c.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL APPROVED BY Raymond Monnin DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 02-07-12 MICROCIRCUIT, MEMORY, DIGITAL, CMOS, FIELD PROGRAMMABLE GATE ARRAY, 32,000 GATES, MONOLITHIC SILICON AMSC N/A SIZE A CAGE CODE 67268 5962

5、-01518 REVISION LEVEL D SHEET 1 OF 21 DSCC FORM 2233 APR 97 5962-E043-07 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-01518 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 2

6、 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying

7、Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 - 01518 01 Q X C | | | | | | | | | | | | | | | | | Federal RHA Device Device Case Lead stock class designator type class outline f

8、inish designator (see 1.2.1) (see 1.2.2) designator (see 1.2.4) (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices

9、 meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 A54SX32A 32,000 gate f

10、ield programmable gate array 1/ 02 A54SX32A-1 32,000 gate field programmable gate array 1/ 2/ 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements documentation M Vendor self-certification t

11、o the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descripti

12、ve designator Terminals Package style X See figure 1 256 Ceramic Quad Flat Pack Y See figure 1 208 Ceramic Quad Flat Pack Z See figure 1 84 Ceramic Quad Flat Pack 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device cl

13、ass M. _ 1/ The A54SX32A and A54SX32A-1 are antifuse-based one-time programmable devices. These devices must be programmed with device manufacturers programming software (see 6.7 herein). 2/ Timing performance of the A54SX32A-1 device shall be approximately 15% faster than the A54SX32A device (End u

14、sers may select the appropriate device speed grade through timing calculations based on device data sheet or timing simulation of specific designs with device manufacturers software (see 6.7 herein) Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STA

15、NDARD MICROCIRCUIT DRAWING SIZE A 5962-01518 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings (for 2.5V/3.3V/5.0V operating conditions). 3/ DC supply voltage range (VCCI) . -0.3 to +6.0 V dc DC supply voltage range (

16、VCCA) -0.3 to +3.0 V dc Input voltage range (VI) -0.5 to +6.0 V dc Output voltage range (VO) -0.5 to (+VCCI+0.5) V dc Storage temperature range (VSTG) -65oC to +150 oC Lead temperature (soldering, 10 seconds) . 300 oC Thermal resistance, junction-to-case (JCfor Cases X, Y, and Z) . 2.0 oC/W Maximum

17、junction temperature (TJ) . 150 oC 1.4 Recommended operating conditions. 3.3V power supply voltage range 3.0 to 3.6 V dc (10% VCCI) 5.0V power supply voltage range 4.5 to 5.5 V dc (10% VCCI) 2.5V power supply voltage range 2.25 to 2.75 V dc (10% VCCA) Case operating temperature range (TC) . -55oC to

18、 +125 oC 1.5 Digital logic testing for device classes Q and V. Fault coverage measurement of manufacturing logic tests (MIL-STD-883, test method 5012) 100 percent 4/ 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks

19、form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFE

20、NSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are a

21、vailable online at http:/assist.daps.dla.mil/quicksearch/ or http:/assist.daps.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Non-Government publications. The following document(s) form a part of this document to the extent

22、 specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. ELECTRONICS INDUSTRIES ASSOCIATION (EIA) JEDEC Standard EIA/JESD78 - IC Latch-Up Test. (Applications for copies should be addressed to the Electronics Industries Association,

23、 2500 Wilson Boulevard, Arlington, VA 22201; http:/www.jedec.org.) (Non-Government standards and other publications are normally available from the organizations that prepare or distribute the documents. These documents also may be available in or through libraries or other informational services.)

24、_ 3/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 4/ 100 percent test coverage of blank programmable logic devices.Provided by IHSNot for ResaleNo reproduction or networki

25、ng permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-01518 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 4 DSCC FORM 2234 APR 97 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references ci

26、ted herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordanc

27、e with MIL-PRF-38535 and as specified herein or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for device class M shall be in accordance with MIL-P

28、RF-38535, appendix A for non-JAN class level B devices and as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein fo

29、r device class M. 3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.4 herein and figure 1. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2. 3.2.3 Truth table(s). 3.2.3.1 Unprogrammed devices. The truth table or test vectors for unprogra

30、mmed devices for contracts involving no altered item drawing is not part of this drawing. When required in screening (see 4.2 herein) or qualification conformance inspection, groups A, B, C, D, or E (see 4.4 herein), the devices shall be programmed by the manufacturer prior to test. A minimum of 90

31、percent of the total number of logic modules shall be utilized. 3.2.3.2 Programmed devices. Prior to submitting altered item drawing the truth table or test vectors for programmed devices should be agreed upon by acquiring activity and the manufacturer. 3.2.4 Test load test circuit. The test load ci

32、rcuit shall be as specified on figure 3. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full case

33、operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical tests for each subgroup are defined in table I. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manu

34、facturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for devic

35、e classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A. 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. The compliance m

36、ark for device class M shall be a “C“ as required in MIL-PRF-38535, appendix A. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For

37、 device class M, a certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this drawing shall affi

38、rm that the manufacturers product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MI

39、L-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product (see 6.2 herein) involving devices acquired to th

40、is drawing is required for any change that affects this drawing. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-01518 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 5 DSCC FO

41、RM 2234 APR 97 3.9 Verification and review for device class M. For device class M, DSCC, DSCCs agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the r

42、eviewer. 3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in microcircuit group number 42 (see MIL-PRF-38535, appendix A). 3.11 Processing options. Since the device is capable of being programmed by either the manufacturer or the user to

43、result in a wide variety of configurations; two processing options are provided for selection in the contract. 3.11.1 Unprogrammed device delivered to the user. All testing shall be verified through group A testing as defined in 4.4.1 and table IIA. 3.11.2 Manufacturer-programmed device delivered to

44、 the user. All testing requirements and quality assurance provisions herein, shall be satisfied by the manufacturer prior to delivery. Manufacturer shall verify design checksum after programming. 4. VERIFICATION 4.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedu

45、res shall be in accordance with MIL-PRF-38535 or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. For device class M, sampling and inspection procedures shall be in accordance with M

46、IL-PRF-38535, appendix A. 4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and shall be conducted on all devices prior to qualification and technology conformance inspection. For device class M, screening shall be in accordance with method 5004 of MIL-S

47、TD-883, and shall be conducted on all devices prior to quality conformance inspection. 4.2.1 Additional criteria for device class M. a. Delete the sequence specified as initial (preburn-in) electrical parameters through interim (postburn-in) electrical parameters of method 5004 and substitute lines

48、1 through 6 of table IIA herein. b. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015. (1) Dynamic burn-in for device class M (method 1015 of MIL-STD-883, test condition D; for circuit, see 4.2.1b herein). c. Interim and final electrical test parameters shall be as specified