DLA DSCC-VID-V62 12623-2012 MICROCIRCUIT DIGITAL MIXED SIGNAL MICROCONTROLLER MONOLITHIC SILICON.pdf

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1、 REVISIONS LTR DESCRIPTION DATE APPROVED Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE 18 19 20 21 REV STATUS OF PAGES REV PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 PMIC N/A PREPARED BY Phu H. Nguyen DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landa

2、ndmaritime.dla.mil/ Original date of drawing YY MM DD CHECKED BY Phu H. Nguyen TITLE MICROCIRCUIT, DIGITAL, MIXED SIGNAL MICROCONTROLLER, MONOLITHIC SILICON 12-12-10 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/12623 REV PAGE 1 OF 21 AMSC N/A 5962-V077-12 Provided by IHSNot fo

3、r ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12623 REV PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance mixed signal microcontroller microcircu

4、it, with an operating temperature range of -40C to +85C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/126

5、23 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 MSP430G2302-EP Mixed signal microcontroller 1.2.2 Case outline(s). The case outlines are as specified herein. Outline letter Number of pin

6、s JEDEC PUB 95 Package style X 14 JEDEC MO-153 Plastic small outline 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladi

7、um Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12623 REV PAGE 3 1.3 Absolute maximum ratings. 1/ Voltage applied at VCCto VSS. -0.3 V to 4.1 V Voltage applied to

8、 any pin -0.3 V to VCC+0.3 V 2/ Diode current at any device terminal 2 mA Storage temperature: 3/ Unprogrammed device -55C to 150C Programmed device -55C to 150C 1.4 Thermal characteristics. Thermal information Case outline X Units Junction to ambient thermal resistance, JA4/ 98.7 C/W Junction to ca

9、se (top) thermal resistance, JCtop5/ 26.8 Junction to board thermal resistance, JB6/ 41.2 Junction to top characterization parameter, JT7/ 1.1 Junction to board characterization parameter, JB8/ 40.5 Junction to case (bottom) thermal resistance, JCbot9/ N/A 1/ Stresses beyond those listed under “abso

10、lute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute maximum rated conditions for ext

11、ended periods may affect device reliability. 2/ All voltage values referenced to VSS. The JTAG fuse blow voltage, VFBis allowed to exceed the absolute maximum rating. The voltage is applied to the TEST pin when blowing the JTAG fuse 3/ Higher temperature may be applied during board soldering accordi

12、ng to the current JEDEC J-STD-020 specification with peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels. 4/ The junction to ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-k-board, as specif

13、ied in JESD51-7, in an environment described in JESD51-2a. 5/ The junction to case (top) thermal resistance is obtanied by simulating a cold plate test on the package top. No specified JEDEC- standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. 6/ The junction

14、 to board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. 7/ The junction to top characterization parameter, JT, estimates the junction teperature of a device in a real system and is extracted fro

15、m the simulation data for obtaining JA, using a procedure described in JESD51-2a (sections 6 and 7). 8/ The junction to board characterization parameter, JB, estimates the junction teperature of a device in a real system and is extracted from the simulation data for obtaining JA, using a procedure d

16、escribed in JESD51-2a (sections 6 and 7). 9/ The junction to case (bottom) thermal resistance is obtanied by simulating a cold plate test on the exposed (power) pad. No specified JEDEC- standard test exists, but a close description can be found in the ANSI SEMI standard G30-88 Provided by IHSNot for

17、 ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12623 REV PAGE 4 1.5 Recommended operating conditions. Supply voltage, (VCC): During program execution . 1.8 V to 3.6 V During flash program/erase

18、. 2.2 V to 3.6 V Supply voltage, (VSS) 0 V Operating free air temperature, (TA) . -40C to 85C Processor frequency (Maximum MCLK frequency) 10/ 11/ VCC= 1.8 V, Duty cycle = 50% 10% dc to 6 MHz VCC= 2.7 V, Duty cycle = 50% 10% dc to 12 MHz VCC= 3.3 V, Duty cycle = 50% 10% dc to 16 MHz 2. APPLICABLE DO

19、CUMENTS JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEP95 Registered and Standard Outlines for Semiconductor Devices JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions Natural Convection (Still Air) JESD51-7 High Effective Thermal Conductivity Test Board for Leaded Surface

20、Mount Packages JESD51-8 Integrated Circuits Thermal Test Method Environment Conditions Junction-to-board J-STD-020 Joint IPC/JEDEC standard for moisture/reflow sensitivity classification for nonhermetic solid state surface mount devices. (Copies of these documents are available online at http:/www.j

21、edec.org or from JEDEC Solid State Technology Association, 3103 North 10th Street, Suite 240S, Arlington, VA 22201.) AMERICAN NATIONAL STANDARDS INSTITUTE (ANSI) STANDARD ANSI SEMI STANDARD G30-88 null Test Method for Junction-to-Case Thermal Resistance Measurements for Ceramic Packages (Application

22、s for copies should be addressed to the American National Standards Institute, Semiconductor Equipment and Materials International, 1819 L Street, NW, 6 th floor, Washington, DC 20036 or online at http:/www.ansi.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the

23、 manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.

24、3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, 1.5 and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein.

25、 _ 10/ The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse width of the specified maximum frequency. 11/ Modules might have different maximum input clock specification. See the specification from the manufacturer data sheet. Provided by IHSNot

26、for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12623 REV PAGE 5 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The ter

27、minal connections shall be as shown in figure 2. 3.5.3 Terminal function. The terminal function shall be as shown in figure 3. 3.5.4 Functional block diagram. The functional block diagram shall be as shown in figure 4. 3.5.5 Safe operating area. The safe operating area shall be as shown in figure 5.

28、 3.5.6 POR/Brownout Reset (BOR) vs Supply voltage. The POR/Brownout Reset (BOR) vs Supply voltage shall be as shown in figure 6. 3.5.7 VCC(drop) level with a Square voltage drop to generate a POR/Brownout signal. The VCC(drop) level with a Square voltage drop to generate a POR/Brownout signal shall

29、be as shown in figure 7. 3.5.8 VCC(drop) level with a Triangle voltage drop to generate a POR/Brownout signal. The VCC(drop) level with a Triangle voltage drop to generate a POR/Brownout signal shall be as shown in figure 8. 3.5.9 DCO wake-up time from LPM3/4 vs DCO frequency. The DCO wake-up time f

30、rom LPM3/4 vs DCO frequency waveforms shall be as shown in figure 9. 3.5.10 USI low level output voltage vs output current. The USI low level output voltage vs output current shall be as shown in figure 10. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS

31、-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12623 REV PAGE 6 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions 2/ 3/ 4/ TAVCCLimits Unit Min Max Active mode supply current into VCCexcluding external current Active mode (AM) current (1 MH

32、z) IAM, 1MHzfDCO= fMCLK= fSMCLK= 1 MHz, fACLK= 32768 Hz, Program executes in flash, BCSCTL1 = CALBC1_1MHz, DCOCTL = CALDCO_1MHz, CPUOFF = 0, SCG0 = 0 SCG1 = 0, OSCOOFF = 0 2.2 V 220 TYP A 3 V 400 Low power mode Supply current (into VCC) Excluding external current Low power mode 0 (LPM0) current 5/ I

33、LPM0, 1MHzfMCLK= 0 MHz, fSMCLK= fCDO= 1 MHz, fACLK= 32,768 Hz, BCSCTL1 = CALBC1_1MHz, DCOCTL = CALDCO_1MHz, CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 25C 2.2 V 55 TYP A Low power mode 2 (LPM2) current 6/ ILPM2fMCLK= fSMCLK= 0 MHz, fCDO= 1 MHz, fACLK= 32,768 Hz, BCSCTL1 = CALBC1_1MHz, DCOCTL = CALDC

34、O_1MHz, CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 25C 2.2 V 22 TYP Low power mode 3 (LPM3) current 6/ ILPM3, LFXT1fDCO= fMCLK= fSMCLK= 0 MHz, fACLK= 32768 Hz, CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 25C 2.2 V 1.0 Low power mode 3 (LPM3) current 6/ ILPM3, VLOfDCO= fMCLK= fSMCLK= 0 MHz, fACLK= fro

35、m internal LF oscillator (VLO), CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 25C 2.2 V 0.7 Low power mode 4 (LPM4) current 7/ ILPM4fDCO= fMCLK= fSMCLK= 0 MHz, fACLK= 0 Hz, CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 25C 2.2 V 0.5 85C 1.5 See footnote at end of table. Provided by IHSNot for ResaleNo rep

36、roduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12623 REV PAGE 7 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Conditions 2/ VCCLimits Unit Min Max Schmitt Trigger inputs (Port P

37、x) 8/ Positive going input threshold voltage VIT+0.45 VCC0.75 VCCV 3 V 1.35 2.25 Negative going input threshold voltage VIT-0.25 VCC0.55 VCC3 V 0.75 1.65 Input voltage hysteresis (VIT+- VIT-) Vhys3 V 0.3 1.0 Pullup/pulldown resistor RPullFor pullup: VIN= VSSFor pulldown: VIN= VCC3 V 20 50 k Input ca

38、pacitance CIVIN= VSSor VCC5 TYP pF Leakage current (Port Px) High impedance leakage current Ilkg(Px.y)9/ 10/ 3 V 50 nA Outputs (Port Px) High level output voltage VOHI(OHmax)= -6 mA 11/ 3 V VCC 0.3 V Low level output voltage VOLI(OLmax)= 6 mA 11/ 3 V VSS+ 0.3 Output frequency (Port Px) Port output f

39、requency (with load) fPx.yPx.y, CL= 20 pF, RL= 1 k 12/ 13/ 3 V 12 TYP MHz Clock output frequency fPortCLKPx.y, CL = 20 pF 13/ 3 V 16 TYP Pin Oscillator frequency Ports Px Port output oscillation frequency foP1.xP1.y, CL= 10 pF, RL= 100 k 14/ 15/ 3 V 1400 TYP kHz P1.y, CL= 20 pF, RL= 100 k 14/ 15/ 90

40、0 TYP Port output oscillation frequency foP2.xP2.0 to P2.5, CL= 10 pF, RL= 100 k 14/ 15/ 3 V 1800 TYP kHz P2.0 to P2.5, CL= 20 pF, RL= 100 k 14/ 15/ 1000 TYP Port output oscillation frequency foP2.6/7P2.6 and P2.7, CL= 20 pF, RL= 100 k 14/ 15/ 3 V 700 TYP kHz POR/Brownout Reset (BOR) 16/ See figure

41、10 VCC(start)dVCC/dt 3 V/s 0.7 x V(B_IT-)TYP V See figure 10 through figure 12 V(B_IT-)dVCC/dt 3 V/s 1.40 TYP V See figure 10 Vhys(B_IT-)dVCC/dt 3 V/s 140 TYP mV See figure 10 td(BOR)2000 s Pulse length needed at RST/NMI pin to accept reset internally t(reset)2.2 V 2 s See footnote at end of table.

42、Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12623 REV PAGE 8 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Conditions 2/ VCCLimits Unit Min

43、 Max DCO frequency Supply voltage VCCRSELx 14 1.8 3.6 V RSELx = 14 2.2 3.6 RSELx = 15 3.0 3.6 DCO frequency (0, 0) fDCO(0,0)RSELx = 0, DCOx = 0, MDDx = 0 3 V 0.06 0.14 MHz DCO frequency (0, 3) fDCO(0,3)RSELx = 0, DCOx = 3, MDDx = 0 3 V 0.07 0.17 DCO frequency (1, 3) fDCO(1,3)RSELx = 1, DCOx = 3, MDD

44、x = 0 3 V 0.15 TYP DCO frequency (2, 3) fDCO(2,3)RSELx = 2, DCOx = 3, MDDx = 0 3 V 0.21 TYP DCO frequency (3, 3) fDCO(3,3)RSELx = 3, DCOx = 3, MDDx = 0 3 V 0.30 TYP DCO frequency (4, 3) fDCO(4,3)RSELx = 4, DCOx = 3, MDDx = 0 3 V 0.41 TYP DCO frequency (5, 3) fDCO(5,3)RSELx = 5, DCOx = 3, MDDx = 0 3

45、V 0.58 TYP DCO frequency (6, 3) fDCO(6,3)RSELx = 6, DCOx = 3, MDDx = 0 3 V 0.54 1.06 DCO frequency (7, 3) fDCO(7,3)RSELx = 7, DCOx = 3, MDDx = 0 3 V 0.80 1.50 DCO frequency (8, 3) fDCO(8,3)RSELx = 8, DCOx = 3, MDDx = 0 3 V 1.6 TYP DCO frequency (9, 3) fDCO(9,3)RSELx = 9, DCOx = 3, MDDx = 0 3 V 2.3 T

46、YP DCO frequency (10, 3) fDCO(10,3)RSELx = 10, DCOx = 3, MDDx = 0 3 V 3.4 TYP DCO frequency (11, 3) fDCO(11,3)RSELx = 11, DCOx = 3, MDDx = 0 3 V 4.25 TYP DCO frequency (12, 3) fDCO(12,3)RSELx = 12, DCOx = 3, MDDx = 0 3 V 4.3 7.30 DCO frequency (13, 3) fDCO(13,3)RSELx = 13, DCOx = 3, MDDx = 0 3 V 6.0

47、0 9.60 DCO frequency (14, 3) fDCO(14,3)RSELx = 14, DCOx = 3, MDDx = 0 3 V 8.6 13.9 DCO frequency (15, 3) fDCO(15,3)RSELx = 15, DCOx = 3, MDDx = 0 3 V 12.0 18.5 DCO frequency (15, 7) fDCO(15,7)RSELx = 15, DCOx = 7, MDDx = 0 3 V 16.0 26.0 Frequency step between range RSEL and RSEL + 1 SRESLSRSEL= fDCO

48、(RSEL+1,DCO)/fDCO(RSEL,DCO)3 V 1.35 TYP ratio Frequency step between tap DCO and DCO + 1 SDCOSDCO= fDCO(RSEL,DCO+1)/fDCO(RSEL,DCO)3 V 1.08 TYP ratio Duty cycle Measured at SMCLK output 3 V 50 TYP % See footnote at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO