DLA DSCC-VID-V62 11621 REV A-2013 MICROCIRCUIT DIGITAL-LINEAR LOW NOISE JFET INPUT OPERATIONAL AMPLIFIER MONOLITHIC SILICON.pdf

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1、 REVISIONS LTR DESCRIPTION DATE APPROVED A Table I, input offset voltage test; with TA= 25C delete 9 mV and substitute 6 mV, with -40C TA 125C, delete 15 mV and substitute 8 mV. Table I, input offset current test, with -40C TA 125C delete 20 nA and substitute 2 nA. Table I, input bias current test,

2、add -40C TA 125C, delete 50 nA and substitute 20 nA. Table I, large signal differential voltage amplification test, add -40C TA 125C for 15 V/mV min limit. Table I, common mode rejection ratio test, delete 75 dB and substitute 80 dB. Table I, slew rate at unity gain test, delete 5 V/s and substitute

3、 8 V/s. - ro 13-01-09 C. SAFFLE Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV A A A A A A A A A A PAGE 1 2 3 4 5 6 7 8 9 10 PMIC N/A PREPARED BY Phu H. Nguyen DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil/ Or

4、iginal date of drawing YY-MM-DD CHECKED BY Phu H. Nguyen TITLE MICROCIRCUIT, DIGITAL-LINEAR, LOW NOISE JFET INPUT OPERATIONAL AMPLIFIER, MONOLITHIC SILICON 11-11-07 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/11621 REV A PAGE 1 OF 10 AMSC N/A 5962-V032-13 Provided by IHSNot f

5、or ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/11621 REV A PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance low noise JFET input operational amp

6、lifier microcircuit, with an operating temperature range of -40C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering docu

7、mentation: V62/11621 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 TL074Q-EP Low noise JFET input operational amplifier 1.2.2 Case outline(s). The case outline(s) are as specified herein.

8、 Outline letter Number of pins JEDEC PUB 95 Package style X 14 JEDEC MS-012 Plastic small outline 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plate C Gold plate D P

9、alladium E Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/11621 REV A PAGE 3 1.3 Absolute maximum ratings. 1/ Maximum supply voltage: 2/ VCC+.

10、18 V VCC-. 18 V Maximum differential input voltage (VID) 30 V 3/ Maximum input voltage (VI) 15 V 2/ 4/ Duration of output short circuit . Unlimited 5/ Maximum package thermal impedance (JA) 86C/W 6/ 7/ Maximum operating virtual junction temperature (TJ) 150C Storage temperature range (Tstg) -65C to

11、150C 2. APPLICABLE DOCUMENTS JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEDEC PUB 95 Registered and Standard Outlines for Semiconductor Devices JEDEC STD 51-7 High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages (Applications for copies should be addressed to the El

12、ectronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or online at http:/www.jedec.org) 1/ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or

13、 any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. 2/ All voltage values, except differential voltages, are with respect to the midpoint between VCC+ a

14、nd VCC-.3/ Differential voltages are at IN+, with respect to IN-. 4/ The magnitude of the input voltage must never exceed the magnitude of the supply voltage or 15 V, whichever is less. 5/ The output may be shorted to ground or to either supply. Temperature and/or supply voltages must be limited to

15、ensure that the dissipation rating is not exceeded. 6/ Maximum power dissipation is a function of TJ(max), JA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD= (TJ(max) TA)/JA. Operating at the absolute maximum TJof 150C can affect reliability. 7/ The packa

16、ge thermal impedance is calculated in accordance with JESD 51-7. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/11621 REV A PAGE 4 3. REQUIREMENTS 3.1 Marking. Parts shall

17、be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and wi

18、th items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physic

19、al dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Symbol diagram. The symbol diagram shall be as shown in figure 3. 3.5.4 Schemat

20、ic diagram. The schematic diagram shall be as shown in figure 4. 3.5.5 Unity gain amplifier. The unity gain amplifier shall be as shown in figure 5. 3.5.6 Gain of 10 inverting amplifier. The gain of 10 inverting amplifier shall be as shown in figure 6. Provided by IHSNot for ResaleNo reproduction or

21、 networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/11621 REV A PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions 2/ 3/ TA4/ Limits Unit Min Max Input offset voltage VIOVO= 0, RS= 50 25C 6 -40

22、C TA 125C 8 Temperature coefficient of input offset voltage VIOVO= 0, RS= 50 -40C TA 125C 18 typical V/C Input offset current IIOVO= 0 25C 100 pA -40C TA 125C 2 nA Input bias current IIBVO= 0 25C 200 pA -40C TA 125C 20 nA Common mode input voltage range VICR25C 11 V Maximum peak output voltage swing

23、 VOMRL= 10 k 25C 12 V RL 10 k -40C TA 125C 12 RL 2 k -40C TA 125C 10 Large signal differential voltage amplification AVDVO= 10 V, RL 2 k 25C 35 V/mV -40C TA 125C 15 Unity gain bandwidth B125C 3 typical MHz Input resistance ri25C 1012typical Common mode rejection ratio CMRR VIC= VICmin, VO= 0, RS= 50

24、 25C 80 dB Supply voltage rejection ratio (VCC/VIO) kSVRVCC= 9 V to 15 V, VO= 0, RS= 50 25C 80 dB Supply current (each amplifier) ICCVO= 0, no load 25C 2.5 mA Crosstalk attenuation VO1/VO2AVD= 100 25C 120 typical dB Operating characteristics. Slew rate at unity gain SR VI= 10 V, RL= 2 k, CL= 100 pF,

25、 see figure 1 25C 8 V/s Rise time overshoot factor trVI= 10 V, RL= 2 k, CL= 100 pF, see figure 1 25C 0.1 typical s 20 typical % Equivalent input noise voltage VnRS= 20 f = 1 kHz 25C 18 typical nV/Hz f = 10 Hz to 10 kHz 4 typical V Equivalent input noise current RS= 20 , f = 1 kHz 25C 0.01 typical pA

26、/Hz Total harmonic distortion THD VIrms = 6 V, AVD= 1, RL 2 k, RS 1 k, f = 1 kHz 25C 0.003 typical % 1/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested acros

27、s the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. 2/ VCC= 15 V (unless otherwise noted). 3/ Input bias currents of an FET input operational amplifier are norm

28、al junction reverse currents, which are temperature sensitive. Pulse techniques must be used that will maintain the junction temperature as close to the ambient temperature as possible. 4/ All characteristics are measured under open-loop conditions with zero common-mode voltage, unless otherwise spe

29、cified. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/11621 REV A PAGE 6 Case X e bD78E E1AA1.004(0.10)SEEDETAIL A.010(0.25)c0-8LDETAIL AGAGEPLANE.010(0.25) MSEATING PLANE

30、114PIN 1INDEX AREADimensions Symbol Inches Millimeters Symbol Inches Millimeters Min Max Min Max Min Max Min Max A .069 1.75 E .150 .157 3.80 4.00 A1 .004 .010 0.10 0.25 E1 .228 .244 5.80 6.20 b .012 .020 0.31 0.51 e .050 BSC 1.27 BSC c .005 .010 0.13 0.25 L .016 .050 0.40 1.27 D .337 .344 8.55 8.75

31、 NOTES: 1. All linear dimensions are in inches. 2. This drawing is subject to change without notice. 3. Body length does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006. inches (0.15 mm) each side. 4. Body width does not include interl

32、ead flash. Interlead flash shall not exceed .017 inche (0.43 mm) each side. 5. Reference JEDEC MS-012 variation AB. FIGURE 1. Case outline. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 162

33、36 DWG NO. V62/11621 REV A PAGE 7 Case outline X Device type 01 Terminal number Terminal symbol Terminal number Terminal symbol 1 1OUT 8 3OUT 2 1IN 9 3IN- 3 1IN+ 10 3IN- 4 VCC+11 VCC-5 2IN+ 12 4IN+ 6 2IN- 13 4IN- 7 2OUT 14 4OUT FIGURE 2. Terminal connections. +-OUTIN+IN-FIGURE 3. Symbol diagram. Pro

34、vided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/11621 REV A PAGE 8 1286464C118 pF1080 1080OUTVCC+VCC-IN+IN-FIGURE 4. Schematic diagram. Provided by IHSNot for ResaleNo reproduc

35、tion or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/11621 REV A PAGE 9 -+VIVOCL= 100 pFRL= 2 kFIGURE 5. Unity gain amplifier. VIVOCL= 100 pFRL-+1 k10 kFIGURE 6. Gain of 10 inverting amplifier. Provided by IHSNot for R

36、esaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/11621 REV A PAGE 10 4. VERIFICATION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requir

37、ements as indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPARATION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling,

38、and marking shall be in accordance with the manufacturers standard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is

39、based on the salient characteristics of the device manufacturers data book. The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein

40、is not to be construed as a guarantee of present or continued availability as a source of supply for the item. DLA Land and Maritime maintains an online database of all current sources of supply at http:/www.landandmaritime.dla.mil/Programs/Smcr/. Vendor item drawing administrative control number 1/

41、 Device manufacturer CAGE code Top side marking Vendor part number V62/11621-01XE 01295 TL074QDR TL074QDREP 1/ The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation. CAGE code Source of supply 01295 Texas Instruments, Inc. Semiconductor Group 8505 Forest Lane P.O. Box 660199 Dallas, TX 75243 Point of contact: U.S. Highway 75 South P.O. Box 84, M/S 853 Sherman, TX 75090-9493 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-