DLA DSCC-VID-V62 09633-2011 MICROCIRCUIT DIGITAL MICROPROCESSOR VOLTAGE MONITORS WITH PROGRAMMABLE VOLTAGE DETECTION MONOLITHIC SILICON.pdf
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1、 REVISIONSLTR DESCRIPTION DATE APPROVEDPrepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV PAGE 1 2 3 4 5 6 7 8 9 10 PMIC N/A PREPARED BY Phu H. Nguyen DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.milOriginal date of drawing YY
2、MM DD CHECKED BY Phu H. Nguyen TITLE MICROCIRCUIT, DIGITAL, MICROPROCESSOR VOLTAGE MONITORS WITH PROGRAMMABLE VOLTAGE DETECTION, MONOLITHIC SILICON 11-07-14 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/09633 REV PAGE 1 OF 10 AMSC N/A 5962-V058-11 Provided by IHSNot for ResaleN
3、o reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09633 REV PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance microprocessor voltage monitor with programmable
4、 voltage detection microcircuit, with an operating temperature range of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engi
5、neering documentation: V62/09633 - 01 X B Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 MAX8211 Microprocessor voltage monitors with programmable voltage detection 02 MAX8212 Microprocessor voltag
6、e monitors with programmable voltage detection 1.2.2 Case outline(s). The case outlines are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 8 JEDEC MS012 Small outline 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by
7、the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plateC Gold plateD PalladiumE Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 1623
8、6 DWG NO. V62/09633 REV PAGE 3 1.3 Absolute maximum ratings. 1/ Supply voltage . -0.5 V to +18 V Output voltage . -0.5 V to +18 V Hysteresis . +0.5 V to -18 V with respect to (V+ + 0.5 V) Threshold input voltage . -0.5 V to (V+ + 0.5 V) Current into any terminal . 50 mA Continuous power dissipation
9、(TA= +70C) Case outline X (derate 5.88 mW/C above +70C) 471 mW Operating temperature range -55C to +125C Storage temperature range . -65C to 150C Lead temperature (soldering , 10 sec) +300C Electro Static Discharge (ESD) Human Body Model (HBM) 800 V Class 1B Moisture Sensitive Level (MSL) . Level 1
10、1.4 Thermal data table. Case outline letter X X Units PC Board Single Layer Multi-Layer 2/ Power dissipation (PD), maximum at +70C 471 588 mW Power dissipation (PD) derating above +70C 5.9 7.4 mW/C Thermal resistance, junction to case (JC) 40 38 C/W Thermal resistance, junction to ambient (JA) 170 1
11、36 C/W 2. APPLICABLE DOCUMENTS JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEDEC PUB 95 Registered and Standard Outlines for Semiconductor Devices JEDEC STD 51-7 High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages (Copies of these documents are available online at h
12、ttp:/www.jedec.org or from JEDEC Solid State Technology Association, 3103 North 10th Street, Suite 240S, Arlington, VA 22201.) 1/ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the dev
13、ice at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ Package thermal resistances were obtained using the method described in JEDEC spec
14、ification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to manufacturer data. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG
15、 NO. V62/09633 REV PAGE 4 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit
16、container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, constru
17、ction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Block diagra
18、m. The block diagram shall be as shown in figure 3. 3.5.4 Threshold trip voltage vs ambient temperature. The threshold trip voltage vs ambient temperature shall be as shown in figure 4. 3.5.5 Basic overvoltage/undervoltage circuit. The basic overvoltage/undervoltage circuit shall be as shown in figu
19、re 5. 3.5.6 Logic supply low voltage detector. The logic supply low voltage detector shall be as shown in figure 6. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09633 REV
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