DLA DSCC-VID-V62 09629 REV A-2010 MICROCIRCUIT DIGITAL FIXED POINT DIGITAL SIGNAL PROCESSOR MONOLITHIC SILICON.pdf

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1、 REVISIONSLTR DESCRIPTION DATE APPROVEDPrepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE 40 41 42 43 44 45 46 47 48 REV PAGE 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 REV STATUS OF PAGES REV PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 PMIC N/A PREPARED B

2、Y Phu H. Nguyen DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil Original date of drawing YY MM DD CHECKED BY Phu H. Nguyen TITLE MICROCIRCUIT, DIGITAL, FIXED POINT DIGITAL SIGNAL PROCESSOR, MONOLITHIC SILICON 10-02-10 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO.

3、 16236 DWG NO. V62/09629 REV PAGE 1 OF 48 AMSC N/A 5962-V016-10 .Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09629 REV PAGE 2 1. SCOPE 1.1 Scope. This drawing

4、documents the general requirements of a high performance Fixed-Point Digital Signal Processor microcircuit, with an operating temperature range of -40C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establ

5、ishes an administrative control number for identifying the item on the engineering documentation: V62/09629 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). 1/ Device type Generic Clock Rat Circuit function 01 SM320C6424-EP 400 MH

6、z Fixed point digital signal Processor 02 SM320C6424-EP 500 MHz Fixed point digital signal Processor 03 SM320C6424-EP 600 MHz Fixed point digital signal Processor 04 SM320C6424-EP 700 MHz Fixed point digital signal Processor 1.2.2 Case outline(s). The case outlines are as specified herein. Outline l

7、etter Number of pins Package style X 376 Plastic ball grid array 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plateC Gold plateD PalladiumE Gold flash palladium Z Ot

8、her 1/ Users are cautioned to review the manufacturers data manual for additional user information relating to this device. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG

9、 NO. V62/09629 REV PAGE 3 1.3 Absolute maximum ratings. 2/ Supply voltage ranges: Core, (CVDD) -0.5 V to +1.5 V 3/ I/O, 3.3 V (DVDD33) . -0.5 V to +4.2 V 3/ I/O, 1.8 V (DVDDR2, DDR_VDDDLL, PLLPWR18, MXVDD) . -0.5 V to +2.5 V 3/ Input voltage ranges: (VI): VI, I/O, 3.3 V pins (except PCI capable pins

10、) . -0.5 V to 4.2 V VI, I/O, 3.3 V pins PCI capable pins -0.5 V to DVDD33+ 0.5 V VI, I/O, 1.8 V -0.5 V to +2.5 V Output voltage ranges: VO, I/O, 3.3 V pins (except PCI capable pins) . -0.5 V to 4.2 V VO, I/O, 3.3 V pins PCI capable pins . -0.5 V to DVDD33+ 0.5 V VO, I/O, 1.8 V . -0.5 V to +2.5 V Ope

11、rating junction temperature ranges, (TJ): Device type: 03 . -40C to +125C Storage temperature range, (TSTG) -65C to +150C 1.4 Recommended operating conditions. 4/ 5/ Supply voltage, core (CVDD): device type 03 . 1.14 V to 1.26 V 6/) Supply voltage, (DVDD): I/O, 3.3 V (DVDD33) . 2.97 V to 3.63 V I/O,

12、 1.8 V (DVDDR2, DDR_VDDDLL, PLLPWR18, MXVDD7/ ) 1.71 V to 1.89 V Supply ground (VSS, DDR_VSSDLL, MXVSS8/) . 0 V DDR2 reference voltage, (DDR_VREF) 9/ 0.49DVDDR2V to 0.51DVDDR2V DDR2 impedance control, connected via 200 resistor to VSS, (DDR_ZP) . VSSTYP DDR2 impedance control, connected via 200 resi

13、stor to DVDDR2, (DDR_ZN) . DVDDR2V TYP High level input voltage, (VIH): 3.3 V (except PCI capable and I2C pins) 2 V minimum MXI/ CLKIN . 0.65MXVDDV minimum PCI 0.5DVDD33to DVDD33+ 0.5 V I2C . 0.7DVDD33V minimum Low level input voltage, (VIL): 3.3 V (except PCI capable and I2C pins) 0.8 V maximum MXI

14、/ CLKIN . 0.35MXVDDV maximum PCI -0.5 V to 0.3DVDD33V I2C . 0.Vto 0.3DVDD33V maximum 2/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond

15、 those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 3/ All voltage values are with respect to VSS. 4/ Use of this product beyond the manufacturers design rules or stated parameters

16、 is done at the users risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. 5/ The actual voltage must be determined at device power-up, and not be changed dynamically during run-time. 6/ Applies to “tape and reel” part number co

17、unterparts as well. For more information, see manufacturer data. 7/ Oscillator 1.8 V power supply (MXVDD) can be connected to the same 1.8 V power supply as DVDDR2. 8/ Oscillator ground (MXVSS) must be kept separate from other grounds and connected directly to the crystal load capacitor ground. 9/ D

18、DR_VREF is expected to equal 0.5VDDR2of the transmitting device and to track variations in the VDDR2. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09629 REV PAG

19、E 4 1.4 Recommended operating conditions - Continued. Operating junction temperature, (TJ) 10/ 11/: Device type 03 . -40C to +125C Operating ambient temperature (TA): 11/ Device type 03 -40C to +85C DSP Operating frequency (FSYSCLK1) 6/ CVDD= 1.2 V: Device type 03 600 MHz CVDD= 1.05 V: Device type 0

20、3 450 MHz Thermal data for case outline X: No C/W 12/ Air Flow (m/s) 13/ 1 Junction to case, RJC 7.7 N/A 2 Junction to board, RJB 10.5 N/A 3 Junction to free air, RJA 19.7 0.00 4 15.5 1.05 14.3 2.007 Junction to package top, PsiJT 4.9 0.00 8 5.1 1.09 5.2 2.0011 Junction to board, PsiJB 10.4 0.00 12

21、9.8 1.013 9.6 2.00_ 10/ In the absence of a heat sink or direct thermal attachment on the top of device, use the following formula to determine the device junction temperature: TJ = TC+ (Power x PsiJT). Power and TCcan be measured by the user. Thermal data for GDU provide the junction to package top

22、 (PsiJT) value based on airflow in the system. In the present of a heat sink or direct thermal attachment on the top of device, additional calculations and considerations must be taken into account. For more detail see manufacturer data. 11/ Applications must meet both the operating junction tempera

23、ture and operating ambient temperature requirements. For more detailed information on thermal considerations, measurements, and calculations, see manufacturer data. 12/ The junction to case measurement was conducted in a JEDEC defined 1SOP system. Other measurements were conducted in a JEDEC defined

24、 1S2P system and will change based on environment as well as application. For more information, see three EIA/JEDEC standards: JEDEC 51-2, JEDEC 51-3, JEDEC 51-7. 13/ m/s = meters per second . Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE S

25、UPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09629 REV PAGE 5 2. APPLICABLE DOCUMENTS JEDEC PUB 95 Registered and Standard Outlines for Semiconductor Devices JEDEC STD 51-2 Integrated Circuits Thermal Test Method Environment Conditions Natural Convection (Still Air)

26、JEDEC STD 51-3 Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages. JEDEC STD 51-7 High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages (Applications for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, A

27、rlington, VA 22201-3834 or online at http:/www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optiona

28、l) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and tab

29、le I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline(s). The case outline(s) shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as

30、 shown in figure 2. 3.5.3 Block diagram. The block diagram shall be as specified in figure 3. 3.5.4 Test load circuit for AC timing measurement. The test load circuit for AC timing measurements shall be as specified in figure 4. 3.5.5 Timing waveforms. The timing waveforms shall be as shown in figur

31、es 5-57. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09629 REV PAGE 6 TABLE I. Electrical performance characteristics. 1/ Test Symbol Test condition 2/ Device

32、type: All Limits Unit Min Max High level output voltage 3.3 V I/O except PCI capable and I2C pins VOHDVDD33= MIN, IOH= MAX 2.4 V 3.3 V I/O PCI capable pins 3/ IOH= -0.5 mA, DVDD33= 3.3 V 0.9DVDD33Low level output voltage 3.3 V I/O except PCI capable and I2C pins VOLDVDD33= MIN, IOL= MAX 0.4 V 3.3 V

33、I/O PCI capable pins 3/ IOH= 1.5 mA, DVDD33= 3.3 V 0.22DVDD333.3 V I/O I2C pins IO= 3 mA 0 0.4 Input current DC 3.3 V pins (except PCI capable and I2C pins) II4/ VI= VSSto DVDD33, pins with internal pullup resistor 5/ 50 250 A VI= VSSto DVDD33, pins with internal pulldown resistor -250 -50 I2C pins

34、VI= VSSto DVDD3310PCI capable pins 6/ 0 VI DVDD33= 3.3 V without internal resistance 50 0 VI DVDD33= 3.3 V without internal pull up resistance 5/ 50 250 0 VI DVDD33= 3.3 V without internal pull down resistance 5/ -250 -50 High level output current DC IOHCLK_OUT0/PWM2/GPIO84 and VLYNQ_CLOCK/PCICLK/GP

35、57 -8 mA DDR2 -13.4PCI capable pins -0.5 3/ All other peripherals -4 Low level output current DC IOLCLK_OUT0/PWM2/GPIO84 and VLYNQ_CLOCK/PCICLK/GP57 8 DDR2 13.4 PCI capable pins 1.5 3/ All other peripherals 4 I/O Off state output current IOZ7/ VO= DVDD33or VSS, internal pull disabled 50 A VO= DVDD33

36、or VSS, internal pull enabled 100 TYP A Core (CVDD) supply current 8/ ICDDCVDD= 1.2 V, DSP clock = 700 MHz 597 TYP mA CVDD= 1.2 V, DSP clock = 600 MHz 524 TYP CVDD= 1.2 V, DSP clock = 500 MHz 460 TYP CVDD= 1.2 V, DSP clock = 400 MHz 392 TYP CVDD= 1.2 V, DSP clock = 560 MHz 442 TYP CVDD= 1.2 V, DSP c

37、lock = 450 MHz 372 TYP CVDD= 1.2 V, DSP clock = 400 MHz 341 TYP See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09629 REV PAGE 7 TAB

38、LE I. Electrical performance characteristics - Continued. 1/ Test Symbol Test condition 2/ Device type: All Limits Unit Min Max 3.3 V I/O (DVDD33) supply current IDDDDVDD= 3.3 V, CVDD= 1.2 V, DSP clock = 700 MHz 13 TYP mA DVDD= 3.3 V, CVDD= 1.2 V, DSP clock = 600 MHz 13 TYP DVDD= 3.3 V, CVDD= 1.2 V,

39、 DSP clock = 500 MHz 13 TYP DVDD= 3.3 V, CVDD= 1.2 V, DSP clock = 400 MHz 13 TYP DVDD= 3.3 V, CVDD= 1.05 V, DSP clock = 560 MHz 13 TYP DVDD= 3.3 V, CVDD= 1.05 V, DSP clock = 450 MHz 13 TYP DVDD= 3.3 V, CVDD= 1.05 V, DSP clock = 400 MHz 13 TYP 1.8 V I/O (DVDDR2, DDR_VDDDLL, PLLVPRW18, MXVDD) supply c

40、urrent IDDDDVDD= 1.8 V, CVDD= 1.2 V, DSP clock = 700 MHz 94 TYP DVDD= 1.8 V, CVDD= 1.2 V, DSP clock = 600 MHz 93 TYP DVDD= 1.8 V, CVDD= 1.2 V, DSP clock = 500 MHz 92 TYP DVDD= 1.8 V, CVDD= 1.2 V, DSP clock = 400 MHz 91 TYP DVDD= 1.8 V, CVDD= 1.05 V, DSP clock = 560 MHz 74 TYP DVDD= 1.8 V, CVDD= 1.05

41、 V, DSP clock = 450 MHz 73 TYP DVDD= 1.8 V, CVDD= 1.05 V, DSP clock = 400 MHz 72 TYP Input capacitance Ci5 pF Output capacitance Co5 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMB

42、US, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09629 REV PAGE 8 TABLE I. Electrical performance characteristics - Continued. 1/ No. Test Symbol Test condition 2/ Device type: All Limits Unit Min Max RESET ELECTRICAL DATA/TIMING Timing requirements for Reset ( See figure 5 and 6) 1 Pulse duration,

43、PORnullnullnullnullnullnulllow or RESETnullnullnullnullnullnullnullnullnulllow tw(RESET) 12C 9/ ns 4 Setup time, boot and configuration pins valid before PORnullnullnullnullnullnullhigh or RESETnullnullnullnullnullnullnullnullnullhigh tsu(CONFIG)12C 9/ 5 Hold time, boot and configuration pins valid

44、after PORnullnullnullnullnullnullhigh or RESETnullnullnullnullnullnullnullnullnullhigh th(CONFIG)0 Switching characteristics during reset 11/ 2 Delay time, PORnullnullnullnullnullnullhigh or RESETnullnullnullnullnullnullnullnullnullhigh to RESETOUTnullnullnullnullnullnullnullnullnullnullnullnullnull

45、nullhigh td(RSTH-RSTOUTH) 1900C ns 3 Pulse duration, SYSCLKs paused (low) before RESETOUTnullnullnullnullnullnullnullnullnullnullnullnullnullnullhigh tw(PAUSE)10C 10C6 Delay time, PORnullnullnullnullnullnulllow or RESETnullnullnullnullnullnullnullnullnulllow to pins invalid td(RSTL-IV) 207 Delay tim

46、e, PORnullnullnullnullnullnullhigh or RESETnullnullnullnullnullnullnullnullnullhigh to pins valid td(RSTH-V) 20 8 Delay time, RESETnullnullnullnullnullnullnullnullnullhigh to pins valid td(RSTOUTH-V) 0 9 Delay time, RESETnullnullnullnullnullnullnullnullnullhigh to pins invalid td(RSTOUTH-IV) 12CEXTE

47、RNAL CLOCK INPUT FROM MXI/CLKIN PIN Input requirement for Crystal 12/ See figure 7 Start up time (from power up until oscillating at stable frequency of 30 MHz) 4 ms Oscillation frequency 15 30 MHz ESR 60 CLOCK PLLs PLLC1 clock frequency ranges MXI/CLKIN 13/ 15 30 MHz PLLOUT Device type 03 CVDD= 1.2

48、 V 300 600 PLLOUT Device type 03 CVDD= 1.05 V 300 520 SYSCLK1 14/ (CLKDIV1 domain) Device type 03 CVDD= 1.2 V 600 SYSCLK1 14/ (CLKDIV1 domain) Device type 03 CVDD= 1.05 V 450 PLLC2 clock frequency ranges MXI/CLKIN 13/ 15 30 MHz PLLOUT At 1.2 V CVDD300 900 At 1.05 V CVDD300 666PLL2_SYSCLK1 (to DDR2 PHY) 333 PLL stabilization/Lock/Reset time PLL stabilization time 150 s PLL lock time 2000C 15/ ns PLL reset time 128C 15