JEDEC JESD61A 01-2007 Isothermal Electromigration Test Procedure.pdf

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1、JEDEC STANDARD Isothermal Electromigration Test Procedure JESD61A.01 (Revision of JESD61A, May 2007) OCTOBER 2007 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board of Directors leve

2、l and subsequently reviewed and approved by the JEDEC legal counsel. JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, and assisting the p

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6、 with this standard may be made unless all requirements stated in the standard are met. Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication should be addressed to JEDEC at the address below, or call (703) 907-7559 or www.jedec.org Published by JEDEC Sol

7、id State Technology Association 2007 2500 Wilson Boulevard Arlington, VA 22201-3834 This document may be downloaded free of charge; however JEDEC retains the copyright on this material. By downloading this file the individual agrees not to charge for or resell the resulting material. PRICE: Please r

8、efer to the current Catalog of JEDEC Engineering Standards and Publications at www.jedec.org Printed in the U.S.A. All rights reserved PLEASE! DONT VIOLATE THE LAW! This document is copyrighted by JEDEC and may not be reproduced without permission. Organizations may obtain permission to reproduce a

9、limited number of copies through entering into a license agreement. For information, contact: JEDEC Solid State Technology Association 2500 Wilson Boulevard Arlington, Virginia 22201-3834 or call (703) 907-7559 JEDEC Standard No. 61A.01 - i - ISOTHERMAL ELECTROMIGRATION TEST PROCEDURE Contents Forew

10、ord. iii Introduction. iii 1 Scope1 2 Normative references .1 3 Terms and definitions.2 4 Symbols4 5 Technical requirements 4 5.1 Equipment requirements6 5.2 Test configuration6 6 The isothermal test algorithm.7 6.1 Initialization phase.8 6.1.1 Measure the resistance at chuck temperature 8 6.1.2 Con

11、vert TCR (Tref) to TCR(Tchuck).9 6.1.3 Initial current value and current multiplication factor.9 6.1.4 Control loop to measure the initial thermal resistance 11 6.1.5 Instrument range and voltage compliance for the initialization phase 11 6.1.6 Temporary failure criterion for the initialization phas

12、e.11 6.1.7 Determination of the initial thermal resistance12 6.2 Temperature staircase and convergence phases 12 6.2.1 Calculate the temperature step and the staircase temperature limit.14 6.2.2 Instrument range and voltage compliance for staircase/convergence/stress phases14 6.2.3 Control loop for

13、the temperature staircase and convergence phases .14 6.2.4 Temporary failure criteria for staircase and convergence phases17 6.3 Stress phase .18 6.3.1 Set the power and the initial current at target stress temperature 19 6.3.2 Calculate the dependence of the resistance on the effective applied powe

14、r19 6.3.3 Control loop to maintain a constant stress temperature.19 6.3.4 Failure criterion for the stress phase20 6.4 Exit at failure of the test line .21 6.4.1 Calculate the time-to-failure (TTF) .21 6.4.2 Required data report 22 6.4.3 Optional data report.22 6.4.4 Optional log file.22 6.5 Isother

15、mal test characteristics23 6.6 Example of isothermal test 24 JEDEC Standard No. 61A.01 - ii - ISOTHERMAL ELECTROMIGRATION TEST PROCEDURE Contents (contd) 7 Interferences.26 7.1 Measurement and control of the wafer temperature 26 7.2 Variation in TCR value26 7.3 Resistance measurements 27 7.4 Feedbac

16、k cycle time 27 7.5 Temperature gradients .28 7.6 Normalization of stress current density .29 7.7 Constant Current Test29 Annex A (normative) ISOT convergence algorithm30 Annex B (normative) Evaluation of the damage during the initial settling time .32 Annex C (informative) Bibliography.35 Annex D (

17、informative) Differences between JESD61A.01 and JESD61A .36 Index .37 Tables Table 1 ISOT input parameters for a copper damascene line 24 Table A.1 Predicted temperature steps in the convergence phase .30 Table A.2 Calculated temperature steps in the convergence phase .31 Table B.1 Calculation of th

18、e fractional damage.33 Table B.2 Dependence of tcorron Eaand n .34 Figures Figure 1 Measurement phases of the isothermal test .7 Figure 2 Flow chart for ISOT initialization phase .10 Figure 3 Flow chart for ISOT temperature staircase and convergence phases 13 Figure 4 Flow chart for ISOT stress phas

19、e 18 Figure 5 Flow chart for ISOT exit-at-failure phase .21 Figure 6 ISOT temperature behavior .24 Figure 7 ISOT resistance behavior.25 Figure 8 ISOT thermal resistance behavior .25 JEDEC Standard No. 61A.01 - iii - Foreword The isothermal test is an accelerated electromigration test performed on mi

20、croelectronic metallizations. In the isothermal test, an attempt is made to maintain a constant mean temperature of the line under test, by varying the stress current and hence the amount of Joule heating imparted to the line. Given a known and unvarying thermal resistance of the sample to the ambie

21、nt, the isothermal test uses a feedback control to maintain a constant power dissipated in the metallization under test, so that a constant test line mean temperature is achieved. When the line resistance changes during the test, due to electromigration damage, the power is kept constant, by varying

22、 the stress current. This document presents an algorithm for conducting the isothermal test using computer-controlled instrumentation. The intent is to provide a complete description of a functional isothermal test algorithm that will allow a programmer to implement and start using an accelerated el

23、ectromigration test with ease. The algorithm is derived from published and unpublished literature. Bibliographic references are listed in Annex C. This standard was formulated under the cognizance of JC-14.2 Committee on Wafer-Level Reliability and approved by the JEDEC Board of Directors (BoD) Ball

24、ot JCB-07-20. It was prepared with the contribution of the National Research Council of Italy, Institute for Microelectronics and Microsystems (CNR-IMM) of Bologna, Italy. The present revision JESD61A introduces significant technical changes from the previous edition (EIA/JESD61, April 1997) to make

25、 it applicable to copper as well as to aluminum metallizations. Substantive changes to the document are listed in Annex D. Introduction As the copper damascene technology has gained widespread use for ULSI interconnections, a renewed interest has developed in fast wafer level reliability (WLR) measu

26、rements to evaluate electromigration. The standard package level reliability (PLR) tests, used in the semiconductor industry, are very expensive when applied to copper metallizations, in comparison with aluminum-based structures, due to the considerable cost of the high temperature environmental cha

27、mbers required (a typical stress temperature is 350 C) and to the time (weeks, months) required to perform some characterizations. Standardized WLR methods, as the Isothermal Test (JESD61) 1, 2, 3, 4, the Standard Wafer level Electromigration Accelerated Test (JEP119A) 5, and the Constant Current Te

28、st (JESD202) have been applied to the evaluation of electromigration in copper, with the aim not to substitute for PLR tests, rather to provide a less expensive tool to complement them: only a wafer prober and some relatively inexpensive measurement instruments are needed. The speed of WLR measureme

29、nts is a key issue in the production line to monitor and give feedback on the quality of the metallization. In this scenario it is fundamental to achieve the best correlation between the PLR and WLR tests 6, 7. The isothermal test has been cited as being the most suitable method 8: a constant and un

30、iform temperature is assumed in the test line, close to the situation achieved in the moderately accelerated constant-current PLR tests. JEDEC Standard No. 61A.01 - iv - Introduction (contd) In fact, the assumption of a uniform temperature in the line during the isothermal test can be a poor approxi

31、mation unless appropriate thermal modeling and test structure designs are used to minimize the unavoidable temperature gradients at the line ends. Hence, when meaningful correlations between PLR and WLR tests results are desired, such efforts are very important. Moreover, it is necessary to enhance

32、the temperature accuracy on copper structures, where temperatures as high as 600 C can be reached during WLR tests. The present revision JESD61A introduces the recommendations for a correct temperature determination 5, 9, 10, previously incorporated in JEP119A (Procedure for SWEAT) and in JESD33B (S

33、tandard for TCR measurement). JEDEC Standard No. 61A.01 Page 1 ISOTHERMAL ELECTROMIGRATION TEST PROCEDURE 1 Scope This document describes a procedure for conducting the ISOthermal accelerated wafer level electromigration Test (ISOT) 1, 2, 3, 4 using computer-controlled instrumentation. This procedur

34、e is suitable for aluminum as well as for copper metallizations. There is no limitation to the use of this procedure at lower acceleration levels, down to and including the levels used for the conventional PLR electromigration test. This document does not specify what test structure to use with this

35、 procedure. A standard describing the design features to be adopted to minimize the temperature gradients (see 7.5) in highly-accelerated WLR measurements is not presently available. However, users of this procedure report its effectiveness with both straight-lines and via-terminated test structures

36、. 2 Normative references The following normative documents contain provisions that, through reference in this text, constitute provisions of this standard. For dated references, subsequent amendments to, or revision of, any of these publications do not apply. However, parties to agreements based on

37、this standard are encouraged to investigate the possibility of applying the most recent editions of the normative references indicated below. For undated references, the latest edition of the normative document referred to applies. JEDEC JESD33B, Standard Method for Measuring and Using the Temperatu

38、re Coefficient of Resistance to Determine the Temperature of a Metallization Line, February 2004. JEDEC JEP119A, A Procedure for Performing SWEAT, August 2003. ASTM F 1259M-96, Standard Guide for Design of Flat, Straight-Line Test Structures for Detecting Metallization Open-Circuit or Resistance-Inc

39、rease Due to Electromigration, Reapproved 2003. JEDEC JESD87, Standard Test Structures for Reliability Assessment of AlCu Metallizations with Barrier Materials, July 2001. JEDEC JESD37, Standard for Lognormal Analysis of Uncensored Data, and of Singly Right-Censored Data Utilizing the Persson and Ro

40、otzen Method, October 1992. JEDEC JESD202, Method for Characterizing the Electromigration Failure Time Distribution of Interconnect Under Constant-Current and Temperature Stress, March 2006. JEDEC Standard No. 61A.01 Page 2 3 Terms and definitions For the purposes of this standard, the following ter

41、ms and definitions apply. 3.1 test structure A passive metallization structure, including a test line, that is fabricated on a semiconductor wafer by procedures used to manufacture microelectronic integrated devices. NOTE Connections are provided to make Kelvin-like resistance measurements of the te

42、st line, i.e., two taps for sensing voltage when two other terminals force a current through the line. Typically, these terminals are located at the ends of the test line in single-level structures, while multi-level structures have vias that connect the ends of the test line to the over- or underly

43、ing metal level in which the terminals are located (see also 7.5). 3.2 test line A metallization line, of specified dimensions, whose length is defined by the position of the two voltage taps for single-level structures or by the position of the vias for multi-level structures, which locate the taps

44、 in a different metal level. NOTE 1 It is assumed that the major portion of the test-line length will have a uniform cross-sectional area. This supports the assumption of approximately uniform temperature along the length. This statement holds true as long as significant voiding has not occurred. Th

45、e assumption is not true at the forcing ends, where a temperature gradient will exist and should be minimized by a proper design in order that the test structure can be suitable for isothermal tests (see 7.5). NOTE 2 The cross-sectional area of the test line may be either the mean geometrical cross-

46、sectional area or the electrical cross-sectional area. The latter is determined by a method (see subclause 6.3.2 of JESD202, 9, 11) based on the knowledge of the parameter T for a given material, e.g., Al or Cu, where is the resistivity of the pure, bulk form of the metal, and T is the temperature.

47、3.3 temperature coefficient of resistance TCR(Tref) C-1 The fractional change in resistance of the test line per unit change in temperature at a specified temperature, Tref, as described in the following equation: ()()refref1TCRRTR TT=(1) where R(Tref) is the resistance of the test line at the refer

48、ence temperature TrefC; R is the change in resistance; T C is the change in temperature that caused the change in resistance. NOTE 1 Two choices of Trefare in common use: 0 C and ambient temperature (typically from 24 to 27 C). They are equivalent as long as self-consistent definitions are used. The

49、 choice of 0 C is preferred, since it facilitates a first-glance comparison of interlaboratory experiments and of experiments conducted at different times in the same laboratory. NOTE 2 For aluminum-based metallizations, the change in resistance of the test line with temperature, R/T, is approximately constant from room temperature to about 420 C. For copper-based metallizations, a variation in R/T value becomes evident at temperatures as low as 200 C 9, 10. Hence, if the TCR is to be use