ETSI TS 102 361-1-2016 Electromagnetic compatibility and Radio spectrum Matters (ERM) Digital Mobile Radio (DMR) Systems Part 1 DMR Air Interface (AI) protocol (V2 4 1)《电磁兼容性和无线电频谱.pdf

《ETSI TS 102 361-1-2016 Electromagnetic compatibility and Radio spectrum Matters (ERM) Digital Mobile Radio (DMR) Systems Part 1 DMR Air Interface (AI) protocol (V2 4 1)《电磁兼容性和无线电频谱.pdf》由会员分享，可在线阅读，更多相关《ETSI TS 102 361-1-2016 Electromagnetic compatibility and Radio spectrum Matters (ERM) Digital Mobile Radio (DMR) Systems Part 1 DMR Air Interface (AI) protocol (V2 4 1)《电磁兼容性和无线电频谱.pdf（177页珍藏版）》请在麦多课文档分享上搜索。

1、 ETSI TS 102 361-1 V2.4.1 (2016-02) Electromagnetic compatibility and Radio spectrum Matters (ERM); Digital Mobile Radio (DMR) Systems; Part 1: DMR Air Interface (AI) protocol TECHNICAL SPECIFICATION ETSI ETSI TS 102 361-1 V2.4.1 (2016-02)2 Reference RTS/ERM-TGDMR-326 Keywords digital, PMR ETSI 650

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7、e copyright and the foregoing restriction extend to reproduction in all media. European Telecommunications Standards Institute 2016. All rights reserved. DECTTM, PLUGTESTSTM, UMTSTMand the ETSI logo are Trade Marks of ETSI registered for the benefit of its Members. 3GPPTM and LTE are Trade Marks of

8、ETSI registered for the benefit of its Members and of the 3GPP Organizational Partners. GSM and the GSM logo are Trade Marks registered and owned by the GSM Association. ETSI ETSI TS 102 361-1 V2.4.1 (2016-02)3 Contents Foreword . 9g3Modal verbs terminology 9g31 Scope 10g32 References 10g32.1 Normat

9、ive references . 10g32.2 Informative references 11g33 Definitions, symbols and abbreviations . 11g33.1 Definitions 11g33.2 Symbols 14g33.3 Abbreviations . 14g34 Overview 16g34.0 Overview introduction 16g34.1 Protocol architecture. 17g34.1.0 Protocol architecture - Introduction 17g34.1.1 Air Interfac

10、e Physical Layer (layer 1). 18g34.1.2 Air Interface Data Link Layer (layer 2) 19g34.1.3 Air Interface Call Control Layer (CCL) (layer 3) . 19g34.2 DMR TDMA structure . 19g34.2.1 Overview of burst and channel structure 19g34.2.2 Burst and frame structure 21g34.3 Frame synchronization . 22g34.4 Timing

11、 references . 24g34.4.1 Repeater mode BS established timing relationship . 24g34.4.2 Repeater mode MS established timing relationship 24g34.4.3 Direct mode timing relationship . 24g34.4.4 TDMA direct mode timing relationship 24g34.5 Common Announcement Channel (CACH) . 24g34.6 Basic channel types 25

12、g34.6.1 Traffic channel with CACH 25g34.6.2 Traffic channel with guard time 26g34.6.3 Bi-directional channel . 26g35 Layer 2 protocol description . 27g35.0 Layer 2 protocol description - Introduction 27g35.1 Layer 2 timing 27g35.1.1 Channel timing relationship 27g35.1.1.0 Channel timing relationship

13、 - Introduction . 27g35.1.1.1 Aligned channel timing . 28g35.1.1.2 Offset channel timing 28g35.1.2 Voice timing . 28g35.1.2.1 Voice superframe 28g35.1.2.2 Voice initiation 29g35.1.2.3 Voice termination 30g35.1.3 Data timing . 30g35.1.3.0 Data timing - Introduction . 30g35.1.3.1 Single slot data timi

14、ng . 30g35.1.3.2 Dual slot data timing . 31g35.1.4 Traffic timing 31g35.1.4.1 BS timing 31g35.1.4.2 Single frequency BS timing 32g35.1.4.3 Direct mode timing . 33g35.1.4.4 Time Division Duplex (TDD) timing 33g35.1.4.5 Continuous transmission mode . 33g35.1.4.6 TDMA direct mode timing 34g35.1.5 Rever

15、se Channel (RC) timing . 34g35.1.5.0 Reverse Channel (RC) timing - Introduction 34g3ETSI ETSI TS 102 361-1 V2.4.1 (2016-02)4 5.1.5.1 Embedded outbound Reverse Channel (RC) . 34g35.1.5.2 Dedicated outbound Reverse Channel (RC) . 35g35.1.5.3 Standalone inbound Reverse Channel (RC) 36g35.1.5.4 Direct m

16、ode Reverse Channel (RC) 36g35.2 Channel access . 37g35.2.0 Channel access - Introduction . 37g35.2.1 Basic channel access rules 38g35.2.1.1 Types of channel activity 38g35.2.1.2 Channel status . 39g35.2.1.3 Timing master . 39g35.2.1.4 Hang time messages and timers 39g35.2.1.5 Slot 1 and 2 dependenc

17、y . 39g35.2.1.6 Transmit admit criteria 40g35.2.1.7 Transmission re-tries . 40g35.2.2 Channel access procedure . 41g35.2.2.0 Channel access procedure - Introduction 41g35.2.2.1 Direct mode Channel Access 41g35.2.2.1.0 Direct mode Channel Access - Introduction 41g35.2.2.1.1 MS Out_of_Sync Channel Acc

18、ess. 41g35.2.2.1.2 MS Out_of_Sync_Channel_Monitored Channel Access . 43g35.2.2.1.3 MS In_Sync_Unknown_System Channel Access . 44g35.2.2.1.4 MS Not_in_Call Channel Access 45g35.2.2.1.5 MS Others_Call Channel Access 45g35.2.2.1.6 MS My_Call Channel Access 45g35.2.2.2 Repeater mode channel access 45g35

19、.2.2.2.0 Repeater mode channel access- Introduction. 45g35.2.2.2.1 MS Out_of_Sync Channel Access. 45g35.2.2.2.2 MS Out_of_Sync_Channel_Monitored Channel Access . 47g35.2.2.2.3 MS In_Sync_Unknown_System channel access . 48g35.2.2.2.4 MS TX_Wakeup_Message 49g35.2.2.2.5 MS Not_In_Call channel access 50

20、g35.2.2.2.6 MS Others_Call channel access 51g35.2.2.2.7 MS My_Call channel access 51g35.2.2.2.8 MS In_Session channel access 51g35.2.2.3 Non-time critical CSBK ACK/NACK channel access 51g35.2.2.4 TDMA direct mode channel access 52g35.2.2.4.0 TDMA direct mode channel access - Introduction 52g35.2.2.4

21、.1 MS Out_of_Sync channel access 52g35.2.2.4.2 MS Out_of_Sync_Channel_Monitored channel access . 55g35.2.2.4.3 MS In_Sync_Unknown_System channel access . 56g35.2.2.4.4 MS Not_in_Call channel access 57g35.2.2.4.5 MS Others_Call channel access 57g35.2.2.4.6 MS My_Call channel access 57g35.2.2.4.7 Imme

22、diate response channel access. 57g36 Layer 2 burst format . 57g36.0 Layer 2 burst format - Introduction 57g36.1 Vocoder socket . 58g36.2 Data and control . 59g36.3 Common Announcement Channel burst . 60g36.4 Reverse Channel . 61g36.4.1 Standalone inbound Reverse Channel burst 61g36.4.2 Outbound reve

23、rse channel (RC) burst . 62g37 DMR signalling 62g37.1 Link Control message structure 62g37.1.0 Link Control message structure - Introduction . 62g37.1.1 Voice LC header . 63g37.1.2 Terminator with LC 64g37.1.3 Embedded signalling. 65g37.1.3.0 Embedded signalling - Introduction 65g37.1.3.1 Outbound c

24、hannel . 65g3ETSI ETSI TS 102 361-1 V2.4.1 (2016-02)5 7.1.3.2 Inbound channel 66g37.1.4 Short Link Control in CACH 66g37.2 Control Signalling BlocK (CSBK) message structure 67g37.2.0 Control Signaling BlocK (CSBK) message structure - Introduction 67g37.2.1 Control Signalling BlocK (CSBK) . 67g37.3 I

25、dle message . 68g37.4 Multi Block Control (MBC) message structure 69g37.4.0 Multi Block Control (MBC) message structure - Introduction . 69g37.4.1 Multi Block Control (MBC) . 70g38 DMR Packet Data Protocol (PDP) . 72g38.0 DMR Packet Data Protocol (PDP) - Introduction 72g38.1 Internet Protocol . 72g3

26、8.2 Datagram fragmentation and re-assembly 73g38.2.0 Datagram fragmentation and re-assembly - Introduction . 73g38.2.1 Header block structure 74g38.2.1.0 Header block structure - Introduction . 74g38.2.1.1 Unconfirmed data Header . 75g38.2.1.2 Confirmed data header 76g38.2.1.3 Response data header 7

27、6g38.2.1.4 Proprietary data header . 76g38.2.1.5 Status/precoded short data header . 77g38.2.1.6 Raw short data header . 78g38.2.1.7 Defined short data header 78g38.2.1.8 Unified Data Transport (UDT) data header. 79g38.2.2 Data block structure 79g38.2.2.0 Data block structure - Introduction . 79g38.

28、2.2.1 Unconfirmed data block structure . 79g38.2.2.2 Confirmed data block structure . 82g38.2.2.3 Response packet format 85g38.2.2.4 Hang time for response packet 86g38.2.2.5 Unified Data Transport (UDT) last data block structure . 87g39 Layer 2 PDU description 88g39.0 Layer 2 PDU description - Intr

29、oduction . 88g39.1 PDUs for voice bursts, general data bursts and the CACH 88g39.1.1 Synchronization (SYNC) PDU . 88g39.1.2 Embedded signalling (EMB) PDU . 89g39.1.3 Slot Type (SLOT) PDU 89g39.1.4 TACT PDU . 90g39.1.5 Reverse Channel (RC) PDU . 90g39.1.6 Full Link Control (FULL LC) PDU 90g39.1.7 Sho

30、rt Link Control (SHORT LC) PDU 90g39.1.8 Control Signalling Block (CSBK) PDU . 91g39.1.9 Pseudo Random Fill Bit (PR FILL) PDU . 91g39.2 Data related PDU description . 91g39.2.0 Data releated PDU description - Introduction . 91g39.2.1 Confirmed packet Header (C_HEAD) PDU . 91g39.2.2 Rate coded packet

31、 Data (R_3_4_DATA) PDU 92g39.2.3 Rate coded Last Data block (R_3_4_LDATA) PDU 92g39.2.4 Confirmed Response packet Header (C_RHEAD) PDU 93g39.2.5 Confirmed Response packet Data (C_RDATA) PDU 93g39.2.6 Unconfirmed data packet Header (U_HEAD) PDU . 93g39.2.7 Rate coded packet Data (R_1_2_DATA) PDU 94g3

32、9.2.8 Rate coded Last Data block (R_1_2_LDATA) PDU 94g39.2.9 Proprietary Header (P_HEAD) PDU 95g39.2.10 Status/Precoded short data packet Header (SP_HEAD) PDU 95g39.2.11 Raw short data packet Header (R_HEAD) PDU 95g39.2.12 Defined Data short data packet Header (DD_HEAD) PDU . 96g39.2.13 Unified Data

33、 Transport Header (UDT_HEAD) PDU . 96g39.2.14 Unified Data Transport Last Data block (UDT_LDATA) PDU . 96g39.2.15 Rate 1 coded packet Data (R_1_DATA) PDU . 97g3ETSI ETSI TS 102 361-1 V2.4.1 (2016-02)6 9.2.16 Rate 1 coded Last Data block (R_1_LDATA) PDU . 97g39.3 Layer 2 information element coding 98

34、g39.3.0 Layer 2 information element coding - Introduction 98g39.3.1 Colour Code (CC) . 98g39.3.2 Pre-emption and power control Indicator (PI) 98g39.3.3 LC Start/Stop (LCSS) . 98g39.3.4 EMB parity . 99g39.3.5 Feature set ID (FID) 99g39.3.6 Data Type 99g39.3.7 Slot Type parity 99g39.3.8 Access Type (A

35、T) . 100g39.3.9 TDMA Channel (TC) 100g39.3.10 Protect Flag (PF) . 100g39.3.11 Full Link Control Opcode (FLCO) . 100g39.3.12 Short Link Control Opcode (SLCO) . 100g39.3.13 TACT parity 100g39.3.14 RC parity . 101g39.3.15 Group or Individual (G/I) . 101g39.3.16 Response Requested (A) . 101g39.3.17 Data

36、 Packet Format (DPF) 101g39.3.18 SAP identifier (SAP) 101g39.3.19 Logical Link ID (LLID) 102g39.3.20 Full message flag (F) 102g39.3.21 Blocks to Follow (BF) 102g39.3.22 Pad Octet Count (POC) . 102g39.3.23 Re-Synchronize Flag (S) . 103g39.3.24 Send sequence number (N(S) 103g39.3.25 Fragment Sequence

37、Number (FSN) 103g39.3.26 Data Block Serial Number (DBSN) 104g39.3.27 Data block CRC (CRC-9) . 104g39.3.28 Class (Class) . 104g39.3.29 Type (Type) 105g39.3.30 Status (Status) . 105g39.3.31 Last Block (LB) 105g39.3.32 Control Signalling BlocK Opcode (CSBKO) . 105g39.3.33 Appended Blocks (AB) . 105g39.

38、3.34 Source Port (SP) . 106g39.3.35 Destination Port (DP) 106g39.3.36 Status/Precoded (S_P). 106g39.3.37 Selective Automatic Repeat reQuest (SARQ) 106g39.3.38 Defined Data format (DD) 106g39.3.39 Unified Data Transport Format (UDT Format) 107g39.3.40 UDT Appended Blocks (UAB) . 108g39.3.41 Supplemen

39、tary Flag (SF) 108g39.3.42 Pad Nibble 108g310 Physical Layer 108g310.1 General parameters . 108g310.1.0 General parameters - Introduction 108g310.1.1 Frequency range 108g310.1.2 RF carrier bandwidth 108g310.1.3 Transmit frequency error 108g310.1.4 Time base clock drift error 109g310.2 Modulation . 1

40、09g310.2.1 Symbols 109g310.2.2 4FSK generation . 109g310.2.2.0 4FSK generation - Introduction. 109g310.2.2.1 Deviation index . 109g310.2.2.2 Square root raised cosine filter 110g310.2.2.3 4FSK Modulator . 110g310.2.3 Burst timing 111g310.2.3.0 Burst timing - Introduction 111g3ETSI ETSI TS 102 361-1

41、V2.4.1 (2016-02)7 10.2.3.1 Normal burst . 111g310.2.3.1.0 Normal burst - Introduction . 111g310.2.3.1.1 Power ramp time 112g310.2.3.1.2 Symbol timing . 113g310.2.3.1.3 Propagation delay and transmission time 113g310.2.3.2 Reverse channel (RC) burst. 114g310.2.3.2.0 Reverse channel (RC) burst - Intro

42、duction 114g310.2.3.2.1 Power ramp time 114g310.2.3.2.2 Symbol timing . 115g310.2.3.2.3 Propagation delay 116g310.2.3.3 Synthesizer Lock-Time constraints . 116g310.2.3.4 Transient frequency constraints during symbol transmission time . 116g3Annex A (normative): Numbering and addressing . 117g3Annex

43、B (normative): FEC and CRC codes 118g3B.0 FEC and CRC codes - Introduction 118g3B.1 Block Product Turbo Codes . 119g3B.1.1 BPTC (196,96) . 119g3B.2 Variable length BPTC 122g3B.2.1 Variable length BPTC for embedded signalling . 122g3B.2.2 Single Burst Variable length BPTC 124g3B.2.2.1 Non-Reverse Cha

44、nnel Single Burst BPTC . 124g3B.2.2.2 Reverse Channel Single Burst BPTC 125g3B.2.3 Variable length BPTC for CACH signalling 126g3B.2.4 Rate Trellis code . 129g3B.2.5 Rate 1 coded data . 133g3B.3 Generator matrices and polynomials 135g3B.3.1 Golay (20,8) . 135g3B.3.2 Quadratic residue (16,7,6) 135g3B

45、.3.3 Hamming (17,12,3) 136g3B.3.4 Hamming (13,9,3), Hamming (15,11,3), and Hamming (16,11,4) . 136g3B.3.5 Hamming (7,4,3) 137g3B.3.6 Reed-Solomon (12,9) . 137g3B.3.7 8-bit CRC calculation . 139g3B.3.8 CRC-CCITT calculation . 140g3B.3.9 32-bit CRC calculation . 140g3B.3.10 CRC-9 calculation 142g3B.3.

46、11 5-bit Checksum (CS) calculation 143g3B.3.12 Data Type CRC Mask 143g3B.3.13 7-bit CRC calculation . 144g3B.4 Interleaving . 145g3B.4.1 CACH interleaving . 145g3Annex C (informative): Example timing diagrams . 146g3C.0 General . 146g3C.1 Direct mode timing . 146g3C.2 Reverse Channel timing . 146g3A

47、nnex D (normative): Idle and Null message bit definition . 147g3D.0 Idle and Null message bit definition - Introduction 147g3D.1 Null embedded message bit definitions 147g3D.2 Idle message bit definitions 148g3Annex E (normative): Transmit bit order . 150g3ETSI ETSI TS 102 361-1 V2.4.1 (2016-02)8 An

48、nex F (normative): Timers and constants in DMR 163g3F.0 Timers and constants in DMR - Introduction . 163g3F.1 Layer 2 timers . 163g3F.2 Layer 2 constants 164g3Annex G (informative): High level states overview . 165g3G.0 High level states overview - Introduction 165g3G.1 High Level MS states and SDL

49、description . 165g3G.1.0 General . 165g3G.1.1 MS Level 1 SDL 165g3G.1.2 MS Level 2 SDL 168g3G.2 High level BS states and SDL descriptions 170g3G.2.0 High level BS states and SDL descriptions - Introduction . 170g3G.2.1 BS Both Slots SDL . 170g3G.2.2 BS Single Slot SDL 171g3Annex H (normative): Feature interoperability 173g3H.0 Feature interoperability - Introduction . 173g3H.1 Feature set ID (FID) . 173g3H.2 Application for Manufacturers Feature set ID . 173g3Annex I (informative): Void . 174g3Annex J (informative): Change requests . 175g3History 177g3ETSI ETSI TS 1