ETSI TS 102 080-2003 Transmission and Multiplexing (TM) Integrated Services Digital Network (ISDN) basic rate access Digital transmission system on metallic local lines (V1 4 1)《传输.pdf
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1、 ETSI TS 102 080 V1.4.1 (2003-07)Technical Specification Transmission and Multiplexing (TM);Integrated Services Digital Network (ISDN) basic rate access;Digital transmission system on metallic local linesETSI ETSI TS 102 080 V1.4.1 (2003-07) 2 Reference RTS/TM-06033 Keywords access, ADSL, basic, cod
2、ing, ISDN, local loop, network, rate, splitter, transmission, VDSL, xDSL ETSI 650 Route des Lucioles F-06921 Sophia Antipolis Cedex - FRANCE Tel.: +33 4 92 94 42 00 Fax: +33 4 93 65 47 16 Siret N 348 623 562 00017 - NAF 742 C Association but non lucratif enregistre la Sous-Prfecture de Grasse (06) N
3、 7803/88 Important notice Individual copies of the present document can be downloaded from: http:/www.etsi.org The present document may be made available in more than one electronic version or in print. In any case of existing or perceived difference in contents between such versions, the reference
4、version is the Portable Document Format (PDF). In case of dispute, the reference shall be the printing on ETSI printers of the PDF version kept on a specific network drive within ETSI Secretariat. Users of the present document should be aware that the document may be subject to revision or change of
5、 status. Information on the current status of this and other ETSI documents is available at http:/portal.etsi.org/tb/status/status.asp If you find errors in the present document, send your comment to: editoretsi.org Copyright Notification No part may be reproduced except as authorized by written per
6、mission. The copyright and the foregoing restriction extend to reproduction in all media. European Telecommunications Standards Institute 2003. All rights reserved. DECTTM, PLUGTESTSTM and UMTSTM are Trade Marks of ETSI registered for the benefit of its Members. TIPHONTMand the TIPHON logo are Trade
7、 Marks currently being registered by ETSI for the benefit of its Members. 3GPPTM is a Trade Mark of ETSI registered for the benefit of its Members and of the 3GPP Organizational Partners. ETSI ETSI TS 102 080 V1.4.1 (2003-07) 3 Contents Intellectual Property Rights9 Foreword.9 1 Scope 10 1.1 Objecti
8、ves.11 2 References 11 3 Definitions and abbreviations.13 3.1 Definitions13 3.2 Abbreviations .13 4 Functions 14 4.1 B-channel .14 4.2 D-channel .14 4.3 Bit timing14 4.4 Octet timing14 4.5 Frame alignment.15 4.6 Activation from LT or NT115 4.7 Deactivation .15 4.8 Power feeding.15 4.9 Operations and
9、 maintenance.15 5 Transmission medium 15 5.1 Description .15 5.2 Minimum ISDN requirements16 5.3 DLL physical characteristics 16 5.4 DLL characteristics 17 5.4.1 Principal characteristics 17 5.4.2 Crosstalk .17 5.4.3 Unbalance about earth 18 5.4.4 Impulse noise 18 5.4.5 Micro interruptions .18 6 Sys
10、tem performance.18 6.1 Performance requirements18 6.1.1 System performance with Regenerators (REGs) 19 6.2 Performance measurements19 6.2.1 DLL physical models19 6.2.2 Intrasystem crosstalk.22 6.2.3 Impulse noise modelling.22 6.2.3.1 Types of impulsive noise 22 6.2.3.2 Measurement arrangement 23 6.2
11、.4 Performance tests23 6.2.4.1 TEST 124 6.2.4.2 TEST 224 6.2.4.3 TEST 324 6.2.5 Micro interruption test 25 6.3 Unbalance about earth25 6.3.1 Longitudinal conversion loss 25 6.3.2 Longitudinal output voltage26 7 Transmission method .27 8 Activation/deactivation 28 8.1 General .28 8.2 Physical represe
12、ntation of signals 28 9 Operation and maintenance28 9.1 Operation and maintenance functions 28 ETSI ETSI TS 102 080 V1.4.1 (2003-07) 4 9.2 CL channel.28 9.2.1 CL channel definition.28 9.2.2 CL channel requirements .29 9.3 Metallic loop testing.29 10 Power feeding.29 10.1 General .29 10.2 Power feedi
13、ng functions.29 10.2.1 Power feeding of the REG 29 10.2.2 Power feeding of the NT1.29 10.2.3 Power feeding of the user network interface 29 10.3 DLL resistance .30 10.4 Wetting current.30 10.5 LT aspects 30 10.5.1 Feeding voltage from the LT 30 10.5.2 Dynamic power feeding requirements 30 10.5.3 LT
14、requirements for the reset of NT1 and REG .31 10.6 Power requirements of NT1 and regenerator .31 10.6.1 Power requirements of NT131 10.6.1.1 Static requirements31 10.6.1.2 Dynamic requirements 32 10.6.2 Power requirement of regenerator 33 10.6.2.1 Static requirements33 10.6.2.2 Dynamic requirements
15、33 10.6.3 Feeding voltage to the NT1 34 10.6.4 Voltage drop across the REG34 10.6.5 Reset of NT1 and REG .34 10.7 Current transient limitation.34 10.8 DC and low frequency AC termination of NT1 and REG34 11 Environmental conditions.34 11.1 Climatic conditions.34 11.2 Safety35 11.3 Overvoltage protec
16、tion.35 11.4 EMC .35 Annex A (normative): Definition of a system using 2B1Q line code36 A.1 Line code36 A.2 Line baud rate.36 A.2.1 NT1 clock tolerance .36 A.2.2 LT clock tolerance36 A.2.3 REG clock tolerance.36 A.3 Frame structure.36 A.3.1 Frame length.37 A.3.2 Bit allocation in direction LT to NT1
17、.37 A.3.3 Bit allocation in direction NT1 to LT.37 A.4 Frame word 38 A.4.1 Frame word in direction LT to NT1.38 A.4.2 Frame word in direction NT1 to LT .38 A.5 Frame alignment procedure38 A.6 Multiframe39 A.6.1 Multiframe word in direction NT1 to LT .39 A.6.2 Multiframe word in direction LT to NT1 .
18、39 A.7 Frame offset between LT to NT1 and NT1 to LT frames 39 A.8 CLchannel 39 A.8.1 Bit rate39 A.8.2 Structure .39 A.8.3 Protocol and procedures .39 ETSI ETSI TS 102 080 V1.4.1 (2003-07) 5 A.8.3.1 Error monitoring function.41 A.8.3.1.1 Cyclic redundancy check 41 A.8.3.1.2 CRC algorithms.41 A.8.3.1.
19、3 Bits covered by the CRC.43 A.8.3.2 Other CL channel functions .43 A.8.3.2.1 Far end block error bit, mandatory43 A.8.3.2.2 The ACT bit, mandatory .43 A.8.3.2.3 The DEA bit, mandatory.43 A.8.3.2.4 NT1 power status bits43 A.8.3.2.5 NT1 Test Mode (NTM) indicator bit 43 A.8.3.2.6 Cold-Start-Only (CSO)
20、 bit 43 A.8.3.2.7 DLL-Only-Activation (UOA) bit43 A.8.3.2.8 S/T-Interface-Activity-Indicator (SAI) bit 43 A.8.3.2.9 Alarm Indicator Bit (AIB).44 A.8.3.2.10 Network Indicator Bit (NIB) for network use .44 A.8.3.2.11 Reserved bits .44 A.8.3.3 Embedded Operations Channel (EOC) functions .44 A.8.3.3.1 E
21、OC frame 44 A.8.3.3.2 Mode of operation.44 A.8.3.3.3 Addressing 45 A.8.3.3.4 Definition of required EOC functions.45 A.8.3.3.5 Codes for required EOC functions 46 A.9 Scrambling .46 A.10 Start-up and control48 A.10.1 Signals used for start-up and control 49 A.10.1.1 Signals during start-up49 A.10.1.
22、2 Line rate during start-up .49 A.10.1.3 Start-up sequence50 A.10.1.4 Wake-up50 A.10.1.5 Progress indicators50 A.10.1.5.1 Start-up50 A.10.1.5.2 Deactivation 51 A.10.2 Timers 51 A.10.3 Description of the start-up procedure .52 A.10.3.1 Start-up from customer equipment .52 A.10.3.2 Start-up from the n
23、etwork.52 A.10.3.3 Sequence charts 52 A.10.3.4 Transparency.54 A.10.4 State transition table for the NT1 .54 A.10.5 State transition table for the LT54 A.10.6 Activation times .61 A.11 Jitter61 A.11.1 NT1 input signal jitter tolerance.61 A.11.2 NT1 output jitter limitations.62 A.11.3 LT input signal
24、 jitter tolerance .63 A.11.4 LT output jitter and synchronization 63 A.11.5 REG jitter tolerance and output jitter limitations .63 A.11.6 Test conditions for jitter measurements63 A.12 Transmitter output characteristics of NT1, REG and LT .63 A.12.1 Pulse amplitude 63 A.12.2 Pulse shape .63 A.12.3 S
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