DLA SMD-5962-94524 REV A-2007 MICROCIRCUIT MEMORY DIGITAL CMOS ONE-TIME PROGRAMMABLE LOGIC ARRAY MONOLITHIC SILICON《硅单片 一次可编程逻辑阵列 氧化物半导体数字记忆微型电路》.pdf

《DLA SMD-5962-94524 REV A-2007 MICROCIRCUIT MEMORY DIGITAL CMOS ONE-TIME PROGRAMMABLE LOGIC ARRAY MONOLITHIC SILICON《硅单片 一次可编程逻辑阵列 氧化物半导体数字记忆微型电路》.pdf》由会员分享，可在线阅读，更多相关《DLA SMD-5962-94524 REV A-2007 MICROCIRCUIT MEMORY DIGITAL CMOS ONE-TIME PROGRAMMABLE LOGIC ARRAY MONOLITHIC SILICON《硅单片 一次可编程逻辑阵列 氧化物半导体数字记忆微型电路》.pdf（20页珍藏版）》请在麦多课文档分享上搜索。

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Boilerplate update, part of 5 year review. ksr 07-03-22 Robert M. Heber THE ORIGINAL FRONT PAGE HAS BEEN REPLACED REV SHET REV A A A A A SHEET 15 16 17 18 19 REV STATUS REV A A A A A A A A A A A A A A OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13

2、 14 PMIC N/A PREPARED BY Kenneth Rice DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY Raj Pithadia COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL APPROVED BY Michael A. Frye DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWI

3、NG APPROVAL DATE 94-01-21 MICROCIRCUIT, MEMORY, DIGITAL, CMOS, ONE-TIME PROGRAMMABLE LOGIC ARRAY, MONOLITHIC SILICON AMSC N/A REVISION LEVEL A SIZE A CAGE CODE 67268 5962-94524 SHEET 1 OF 19 DSCC FORM 2233 APR 97 5962-E203-07 Provided by IHSNot for ResaleNo reproduction or networking permitted witho

4、ut license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-94524 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes

5、 Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. 1.2 PIN. The PIN is as shown in the f

6、ollowing example: 5962 - 94524 01 M L A Federal RHA Device Device Case Lead stock class designator type class outline finish designator (see 1.2.1) (see 1.2.2) designator (see 1.2.4) (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the M

7、IL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device

8、type(s) identify the circuit function as follows: Device type Generic number Circuit function Address access time 01 V750 22-input 10-output and-or-logic array 35 ns 02 V750 22-input 10-output and-or-logic array 25 ns 03 V750 22-input 10-output and-or-logic array 20 ns 04 V750L 22-input 10-output an

9、d-or-logic array 30 ns 05 V750L 22-input 10-output and-or-logic array 25 ns 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements documentation M Vendor self-certification to the requirements

10、 for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Term

11、inals Package style L GDIP3-T24, CDIP4-T24 24 dual-in-line package 3 CQCC1-N28 28 square chip carrier package 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. Provided by IHSNot for ResaleNo reproduction o

12、r networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-94524 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 1/ Supply voltage range - -0.5 V dc to +7.0 V dc Input voltage ran

13、ge- -2.0 V dc to +7.0 V dc 2/ Output voltage applied - -0.5 V dc to +7.0 V dc 2/ Output sink current - 16 mA Thermal resistance, junction-to-case (JC)- See MIL-STD-1835 Maximum power dissipation (PD) 3/- 1.2 W Maximum junction temperature - +175C Lead temperature (soldering, 10 seconds maximum) - +3

14、00C Data retention- 20 years (minimum) 1.4 Recommended operating conditions. Supply voltage (VCC) - 4.5 V dc to 5.5 V dc High level input voltage (VIH) - 2.0 V dc minimum Low level input voltage (VIL)- 0.8 V dc maximum Case operating temperature range (TC) - -55C to +125C 2. APPLICABLE DOCUMENTS 2.1

15、 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPEC

16、IFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Stan

17、dard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/assist.daps.dla.mil/quicksearch/ or http:/assist.daps.dla.mil from the Standardization Document Order Desk, 700 Robins Avenue, Building 4D, Philadelphia, PA 19111-5094.

18、) 2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation. AMERICAN SOCIETY FOR TESTING AND MATERIALS (ASTM) ASTM Standard F1192-00 - Standard

19、 Guide for the Measurement of Single Event Phenomena from Heavy Ion Irradiation of Semiconductor Devices. (Applications for copies of ASTM publications should be addressed to: ASTM International, PO Box C700, 100 Barr Harbor Drive, West Conshohocken, PA 19428-2959; http:/www.astm.org.) 1/ All voltag

20、es referenced to VSS. 2/ Minimum voltage is -0.6 V dc which may undershoot to -2.0 V dc for pulses of less than 20 ns. Maximum output pin voltage is VCC+0.75 V dc which may overshoot to +7.0 V dc for pulses of less than 20 ns. 3/ Must withstand the added PDdue to short circuit test, e.g., IOS. Provi

21、ded by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-94524 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 4 DSCC FORM 2234 APR 97 ELECTRONICS INDUSTRIES ASSOCIATION (EIA) JEDEC Standard

22、 EIA/JESD78 - IC Latch-Up Test. (Applications for copies should be addressed to the Electronics Industries Association, 2500 Wilson Boulevard, Arlington, VA 22201; http:/www.jedec.org.) (Non-Government standards and other publications are normally available from the organizations that prepare or dis

23、tribute the documents. These documents also may be available in or through libraries or other informational services.) 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this docu

24、ment, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device m

25、anufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified her

26、ein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outline(s). The case outline(s) shall be in ac

27、cordance with 1.2.4 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table. 3.2.3.1 Unprogrammed devices. The truth table for unprogrammed devices for contracts involving no altered item drawing shall be as specified on figure 2. When requir

28、ed in group A, B, or C inspections (see 4.3), the device shall be programmed by the manufacturer prior to test with a minimum of 50 percent of the total number of gates programmed or to any altered item drawing pattern which includes at least 25 percent of the total number of gates programmed. 3.2.3

29、.2 Programmed devices. The truth table for programmed devices shall be as specified by an attached altered item drawing. 3.2.4 Logic block diagram. The logic block diagram shall be as specified in figure 3. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless other

30、wise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in ta

31、ble IIA. The electrical tests for each subgroup are defined in table I. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, th

32、e manufacturer has the option of not marking the “5962-“ on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in accordance with MIL-PRF-38535, app

33、endix A. 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. The compliance mark for device class M shall be a “C“ as required in MIL-PRF-38535, appendix A. Provided by IHSNot for ResaleNo reproduction or networ

34、king permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-94524 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 5 DSCC FORM 2234 APR 97 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required

35、 from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6.2 herein). The certifi

36、cate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturers product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A a

37、nd herein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Processing options. Since the device is c

38、apable of being programmed by either the manufacturer or the user to result in a wide variety of configurations; two processing options are provided for selection in the contract. 3.8.1 Unprogrammed device delivered to the user. All testing shall be verified through group A testing as defined in 3.2

39、.3.1 and table IIA. It is recommended that users perform subgroups 7 and 9 after programming to verify the specific program configuration. 3.8.2 Manufacturer-programmed device delivered to the user. All testing requirements and quality assurance provisions herein, including the requirements of the a

40、ltered item drawing, shall be satisfied by the manufacturer prior to delivery. 3.8.3 Verification of erasure or programmability of the device. When specified, devices shall be verified as either programmed to the specified pattern or erased. As a minimum, verification shall consist of performing a f

41、unctional test (subgroup 7) to verify that all bits are in the proper state. Any bit that does not verify to be in the proper state shall constitute a device failure, and shall be removed from the lot. 3.9 Data retention. A data retention stress test shall be completed as part of the vendors reliabi

42、lity process. This test shall be done initially and after any design or process change which may affect data retention. The methods and procedures may be vendor specific, but will guarantee the number of years listed in section 1.3 herein. The vendors procedure shall be under document control and sh

43、all be made available upon request. Data retention capability shall be guaranteed over the full military temperature range. 3.10 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product (see 6.2 herein) involving devices acquired to this drawing is

44、required for any change that affects this drawing. 3.11 Verification and review for device class M. For device class M, DSCC, DSCCs agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made ava

45、ilable onshore at the option of the reviewer. 3.12 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in microcircuit group number 42 (see MIL-PRF-38535, appendix A). Provided by IHSNot for ResaleNo reproduction or networking permitted without l

46、icense from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-94524 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Limits Test Symbol Conditions 1/ 4.5 V VCC 5.5 V -55C TC +125C Unless otherwise

47、 specified Group A Subgroups Device types Min Max Unit High level output voltage VOHIO= - 4.0 mA 1,2,3 All 2.4 V Low level output voltage VOLIO= 8.0 mA 1,2,3 All 0.5 V High impedance 2/ output leakage current IOZVCC= 5.5 V, VO= 5.5 V, VO= GND 1,2,3 All -10 10 A VIH= 5.5 V 1,2,3 All 25 High level input current IIHVIH= 2.4 V 1,2,3 All 10 A VIH= 0.4 V 1,2,3 All -10 Low level input current IIL