DLA SMD-5962-92153 REV M-2006 MICROCIRCUIT DIGITAL CMOS 32K X 8 STATIC RANDOM ACCESS MEMORY (SRAM) MONOLITHIC SILICON《硅单块 32K X8静态随机存取存储器 互补金属氧化物半导体 数字微型电路》.pdf

《DLA SMD-5962-92153 REV M-2006 MICROCIRCUIT DIGITAL CMOS 32K X 8 STATIC RANDOM ACCESS MEMORY (SRAM) MONOLITHIC SILICON《硅单块 32K X8静态随机存取存储器 互补金属氧化物半导体 数字微型电路》.pdf》由会员分享，可在线阅读，更多相关《DLA SMD-5962-92153 REV M-2006 MICROCIRCUIT DIGITAL CMOS 32K X 8 STATIC RANDOM ACCESS MEMORY (SRAM) MONOLITHIC SILICON《硅单块 32K X8静态随机存取存储器 互补金属氧化物半导体 数字微型电路》.pdf（36页珍藏版）》请在麦多课文档分享上搜索。

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Update boilerplate. Add devices 02 through 12. Add case outlines Z, U, T, and M. Add CAGE 52088 as source of supply for devices 02 through 04, CAGE 31468 as source of supply for devices 05 through 08, and CAGE 65342 as source of supply for device

2、s 09 through 12. Editorial changes throughout. 93-09-16 M.A. Frye B Changes in accordance with NOR 5962-R044-94. 94-01-05 M.A. Frye C Changes in accordance with NOR 5962-R197-94. 94-05-20 M.A. Frye D Update boilerplate. Add devices 13 and 14. Add case outlines P and 9. Add CAGE 52088 as source of su

3、pply for devices 13 and 14. Editorial changes throughout. 94-06-24 M.A. Frye E Changes in accordance with NOR 5962-R259-94. 94-08-08 M.A. Frye F Update boilerplate. Make corrections to table IB. Add device types 15 through 18 and CAGE 65342 as source of supply. Add device type 19 and CAGE 34168 as s

4、ource of supply. Editorial changes throughout. 95-11-17 M.A. Frye G Changes in accordance with NOR 5962-R097-96 96-04-11 M.A. Frye H Changes in accordance with NOR 5962-R122-96 96-05-06 M.A. Frye J Changes in accordance with NOR 5962-R239-97 97-03-31 Raymond Monnin K Updated boilerplate. Added case

5、outline “4“. Corrected terminal connection pinouts for case outlines “Z“ and “U“. glg 97-08-27 Raymond Monnin L Added pin 1 index indicator for case outlines “N“. - ksr 00-10-17 Raymond Monnin M Boilerplate update and part of five year review. tcr 06-08-01 Raymond Monnin REV SHET REV M M M M M M M M

6、 M M M M M M M M M M SHEET 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 REV STATUS REV M M M M M M M M M M M M M M OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Jeffery D. Bowling DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY Ray Monnin COLU

7、MBUS, OHIO 43218-3990 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Michael A. Frye MICROCIRCUIT, DIGITAL, CMOS, 32K X 8 STATIC RANDOM ACCESS MEMORY (SRAM), MONOLITHIC SILICON AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 92-09-30 AMSC N/A

8、REVISION LEVEL M SIZE A CAGE CODE 67268 5962-92153 SHEET 1 OF 32 DSCC FORM 2233 APR 97 5962-E549-06 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-92153 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-39

9、90 REVISION LEVEL M SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected

10、in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 - 92153 01 Q X X Federal stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2)Devic

11、e class designatorCase outline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the

12、 MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number 1/ Circuit function Input/output levels Chip enable

13、 2/ Access time 01 LOR2568C 32K X 8 CMOS SRAM CMOS Dual 60 ns 02 LOR2568T 32K X 8 CMOS SRAM TTL Dual 60 ns 03 LOR2568C 32K X 8 CMOS SRAM CMOS Dual 40 ns 04 LOR2568T 32K X 8 CMOS SRAM TTL Dual 40 ns 05 HC6856 32K X 8 CMOS SRAM CMOS Dual 60 ns 06 HC6856 32K X 8 CMOS SRAM TTL Dual 60 ns 07 HC6856 32K X

14、 8 CMOS SRAM CMOS Dual 40 ns 08 HC6856 32K X 8 CMOS SRAM TTL Dual 40 ns 09 UT7156C55PB 32K X 8 CMOS SRAM CMOS Single 55 ns 10 UT7156T55PB 32K X 8 CMOS SRAM TTL Single 55 ns 11 UT7156C55WB 32K X 8 CMOS SRAM CMOS Dual 55 ns 12 UT7156T55WB 32K X 8 CMOS SRAM TTL Dual 55 ns 13 LOR2568C 32K X 8 CMOS SRAM

15、CMOS Dual 30 ns 14 LOR2568T 32K X 8 CMOS SRAM TTL Dual 30 ns 15 UT7156C70PB 32K X 8 CMOS SRAM CMOS Single 70 ns 16 UT7156T70PB 32K X 8 CMOS SRAM TTL Single 70 ns 17 UT7156C70WB 32K X 8 CMOS SRAM CMOS Dual 70 ns 18 UT7156T70WB 32K X 8 CMOS SRAM TTL Dual 70 ns 19 HC6856 32K X 8 CMOS SRAM CMOS Dual 35

16、ns 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accord

17、ance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535 1/ Generic numbers are also listed on the Standard Microcircuit Drawing Source Approval Bulletin at the end of this document and will also be listed in MIL-HDBK-103 and QML-38535. 2/ Any device type, when ord

18、ered in case outline “M“ or “9“, is single chip enable. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-92153 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL M SHEET 3 DSCC FORM 2234 A

19、PR 97 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style X See figure 1 36 Flat pack Y See figure 1 40 Flat pack Z See figure 1 36 Flat pack U See figure 1 36 Flat pack T See figure 1 36 Flat pack

20、 M GDIP1-T28 or CDIP2-T28 28 Dual-in-line N See figure 1 36 Flat pack 9 See figure 1 28 Flat pack 4 See figure 1 36 Flat pack 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. 1.3 Absolute maximum ratings.

21、3/ 4/ Supply voltage range (VCC) - -0.5 V dc to +7.0 V dc DC input voltage range (VIN) - -0.5 V dc to VCC+ 0.3 V dc DC output voltage range (VOUT) - -0.5 V dc to VCC+ 0.3 V dc Storage temperature range - -65C to +150C Lead temperature (soldering, 5 seconds) - +250C Thermal resistance, junction-to-ca

22、se (JC): Cases X and Y - 3.3C/watt Cases Z, U, and 4 - 2.2C/watt. Case T - 10C/watt Case M - See MIL-STD-1835 Case N - 2.1C/watt Case 9 - 1.8C/watt Output voltage applied to high Z state - -0.3 V dc to VCC+ 0.3 V dc Maximum power dissipation (PD) - 2 watts Maximum junction temperature (TJ) - +150C 5

23、/ 1.4 Recommended operating conditions. Supply voltage range (VCC) - 4.5 V dc (min) to 5.5 V dc (max) Supply voltage (VSS) - 0.0 V dc High level input voltage range (VIH): Device types 01,03,09,11,13,15,17 (CMOS levels) - 3.5 V dc to VCC+ 0.3 V dc Device types 05,07,19 (CMOS levels) - 0.7 x VCCto VC

24、C+ 0.3 V dc Device types 02,04,06,08,10,12,14,16,18 (TTL levels) - 2.2 V dc to VCC+ 0.3 V dc Low level input voltage range (VIL): Device types 01,03,09,11,13,15,17 (CMOS levels) - -0.3 V dc to 1.5 V dc Device types 05,07,19 (CMOS levels) - -0.3 V dc to 0.3 x VCCDevice types 02,04,06,08,10,12,14,16,1

25、8 (TTL levels) - -0.3 V dc to 0.8 V dc Case operating temperature range (TC) - -55C to +125C 1.5 Digital logic testing for device classes Q and V. Fault coverage measurement of manufacturing logic tests (MIL-STD-883, method 5012) - 100 percent 2. APPLICABLE DOCUMENTS 2.1 Government specification, st

26、andards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. _ 3/ Stresses above the absolute maximum rating may cau

27、se permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 4/ All voltages referenced to VSS(VSS= ground), unless otherwise specified. 5/ Maximum junction temperature may be increased to +175C during burn-in and steady-state life.Provi

28、ded by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-92153 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL M SHEET 4 DSCC FORM 2234 APR 97 DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Int

29、egrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. M

30、IL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/assist.daps.dla.mil/quicksearch/ or http:/assist.daps.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Non-Government publ

31、ications. The following documents form a part of this document to the extent specified herein. Unless otherwise specified, the issues of the documents are the issues of the documents cited in the solicitation. AMERICAN SOCIETY FOR TESTING AND MATERIALS (ASTM) ASTM Standard F1192-00 - Standard Guide

32、for the Measurement of Single Event Phenomena (SEP) induced by Heavy Ion Irradiation of Semiconductor Devices. (Applications for copies of ASTM publications should be addressed to: ASTM International, PO Box C700, 100 Barr Harbor Drive, West Conshohocken, PA 19428-2959; http:/www.astm.org.) ELECTRON

33、ICS INDUSTRIES ALLIANCE (EIA) JEDEC Standard EIA/JESD 78 - IC Latch-Up Test. (Applications for copies should be addressed to the Electronics Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201; http:/www.jedec.org.) (Non-Government standards and other publications are normally available

34、from the organizations that prepare or distribute the documents. These documents also may be available in or through libraries or other informational services.) 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this draw

35、ing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 and as speci

36、fied herein or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN

37、class level B devices and as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outl

38、ine(s). The case outline(s) shall be in accordance with 1.2.4 herein and figure 1. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2. 3.2.3 Truth table(s). The truth table(s) shall be as specified on figure 3 3.2.4 Radiation exposure circuit. The radiation exposu

39、re circuit shall be as specified on figure 6. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-92153 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL M SHEET 5 DSCC FORM 2234 APR 97 3.2.

40、5 Functional tests. Various functional tests used to test this device are contained in the appendix. If the test patterns cannot be implemented due to test equipment limitations, alternate test patterns to accomplish the same results shall be allowed. For device class M, alternate test patterns shal

41、l be maintained under document revision level control by the manufacturer and shall be made available to the preparing or acquiring activity upon request. For device classes Q and V alternate test patterns shall be under the control of the device manufacturers Technology Review Board (TRB) in accord

42、ance with MIL-PRF-38535 and shall be made available to the preparing or acquiring activity upon request. 3.2.6 Die overcoat. Polyimide and silicone coatings are allowable as an overcoat on the die for alpha particle protection only. Each coated microcircuit inspection lot (see inspection lot as defi

43、ned in MIL-PRF-38535) shall be subjected to and pass the internal moisture content test at 5000 ppm (see method 1018 of MIL-STD-883). The frequency of the internal water vapor testing shall not be decreased unless approved by the preparing activity for class M. The TRB will ascertain the requirement

44、s as provided by MIL-PRF-38535 for classes Q and V. Samples may be pulled any time after seal. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specifi