DLA SMD-5962-90803 REV D-2012 MICROCIRCUIT MEMORY DIGITAL CMOS 8K X 8-BIT PROM MONOLITHIC SILICON.pdf
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1、REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Update drawing to reflect current requirements. Editorial changes throughout. - gap 01-02-15 Raymond Monnin B Boilerplate update and part of five year review. tcr 07-01-29 Joseph Rodenbeck C Correction to Table I; ICC2 remove devices 05-07 and 08
2、from the device type column. ksr 07-06-11 Robert M. Heber D Sheet 10, FIGURE 4, Output Load Circuit values, change R1value for device types 4 and 8 from 658 ohms to 250 ohms, and R2from 403 ohms to 167 ohms. Boilerplate changes as needed. - glg 12-03-14 Charles Saffle THE ORIGINAL FIRST PAGE OF THIS
3、 DRAWING HAS BEEN REPLACED. REV SHEET REV D SHEET 15 REV STATUS REV D D D D D D D D D D D D D D OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Gary L. Gross DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY Ray Monnin COLUMBUS, OHIO 43218-3990 http:/www.l
4、andandmaritime.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE APPROVED BY Michael A. Frye MICROCIRCUIT, MEMORY, DIGITAL, CMOS 8K X 8-BIT PROM, MONOLITHIC SILICON DRAWING APPROVAL DATE 92-07-20 AMSC N/A REVISION LEVEL D SIZE A CAGE CODE 67268 59
5、62-90803 SHEET 1 OF 14 DSCC FORM 2233 APR 97 5962-E091-12 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90803 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 2 DSCC FORM 2234 APR 97 1
6、. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When avail
7、able, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 - 90803 01 M X X Federal stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2) Device class designator Case outline (see 1.2.4) Lead f
8、inish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels a
9、nd are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function Access time 01 7C261 8K X 8-bit PROM 55 ns 02 7C261 8K X 8-bit PROM 45 ns 03 7C261
10、8K X 8-bit PROM 35 ns 04 7C261 8K X 8-bit PROM 25 ns 05 7C263, 7C264 8K X 8-bit PROM 55 ns 06 7C263, 7C264 8K X 8-bit PROM 45 ns 07 7C263, 7C264 8K X 8-bit PROM 35 ns 08 7C263, 7C264 8K X 8-bit PROM 25 ns 1.2.3 Device class designator. The device class designator is a single letter identifying the p
11、roduct assurance level as follows: Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535 1.2.4
12、Case outlines. The case outlines are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style J GDIP1-T24 or CDIP2-T24 24 Dual-in-line K GDFP2-F24 or CDFP3-F24 24 Flat pack L GDIP3-T24 or CDIP4-T24 24 Dual-in-line 3 CQCC1-N28 28 Square leadless chip
13、 carrier 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90803 D
14、LA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 1/ Supply voltage range to ground potential (VCC) -0.5 V dc to +7.0 V dc DC voltage applied to the outputs in the high-Z state . -0.5 V dc to +7.0 V dc DC input voltage . -3.0
15、V dc to +7.0 V dc DC program voltage 13.0 V dc Maximum power dissipation . 1.0 W 2/ Lead temperature (soldering, 10 seconds) +260C Thermal resistance, junction-to-case (JC) See MIL-STD-1835 Junction temperature (TJ) +175C Storage temperature range (TSTG) -65C to +150C 1.4 Recommended operating condi
16、tions. Supply voltage (VCC) . +4.5 V dc minimum to +5.5 V dc maximum Ground voltage (GND) 0 V dc Input high voltage (VIH) . 2.0 V dc minimum Input low voltage (VIL) . 0.8 V dc maximum 3/ Case operating temperature range (TC) -55C to +125C 2. APPLICABLE DOCUMENTS 2.1 Government specification, standar
17、ds, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrat
18、ed Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HD
19、BK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) _ 1/ Stresses above the absolute maximum rating may caus
20、e permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2/ Must withstand the added PDdue to short circuit test; e.g., IOS. 3/ VILnegative undershoots to a minimum of -3.0 V dc are allowed for pulse widths VIH1, 2, 3 01-03 30 mA IOUT
21、= 0 mA 04 50 Input capacitance 3/ CINVCC= 5.0 V, VIN= 0 V 4 All 10 pF TA= +25C, f = 1 MHz (see 4.4.1d) Output capacitance 3/ COUTVCC= 5.0 V, VOUT= 0 V 4 All 10 pF TA= +25C, f = 1 MHz (see 4.4.1d) Functional tests See 4.4.1c 7, 8 All Address to output valid tAASee figures 3 and 4 and 9, 10, 11 01, 05
22、 55 ns note 5/ 02, 06 45 03, 07 35 04, 08 25 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90803 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 7 DSCC
23、FORM 2234 APR 97 TABLE I. Electrical performance characteristics Continued. Test Symbol Conditions -55C TC +125C 4.5 V VCC 5.5 V Group A subgroups Device type Limits Unit unless otherwise specified Min Max Chip select active to tACSSee figures 3 and 4 and 9, 10, 11 01 55 ns output valid note 5/ 02 4
24、5 03 40 04 25 05 35 06 30 07 20 08 15 Chip select active to tPU9, 10, 11 01-04 0 ns power-up 3/ Chip select inactive to tPD9, 10, 11 01 55 ns power-down 3/ 02 45 03 35 04 25 Chip select inactive tHZCSSee figures 3 and 4 and 9, 10, 11 01 55 ns to high-Z 3/ note 5/ and 6/ 02 45 03, 05 35 04, 07 25 06
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