DLA SMD-5962-89715 REV B-1998 MICROCIRCUIT DIGITAL CMOS IMAGE RESAMPLING SEQUENCER MONOLITHIC SILICON《硅单片 图象重采样序列发生器 氧化物半导体数字微型电路》.pdf

《DLA SMD-5962-89715 REV B-1998 MICROCIRCUIT DIGITAL CMOS IMAGE RESAMPLING SEQUENCER MONOLITHIC SILICON《硅单片 图象重采样序列发生器 氧化物半导体数字微型电路》.pdf》由会员分享，可在线阅读，更多相关《DLA SMD-5962-89715 REV B-1998 MICROCIRCUIT DIGITAL CMOS IMAGE RESAMPLING SEQUENCER MONOLITHIC SILICON《硅单片 图象重采样序列发生器 氧化物半导体数字微型电路》.pdf（17页珍藏版）》请在麦多课文档分享上搜索。

1、REVISIONSLTR DESCRIPTION DATE (YR-MO-DA) APPROVEDA Change in accordance with NOR 5962-R076-96. 96-04-11 Monica L. PoelkingB Add device type 03. Update boilerplate. Editorial changes throughout. - tvn 98-09-18 Monica L. PoelkingREVSHEETREV B BSHEET 15 16REV STATUS REV B B B B B B B B B B B B B BOF SH

2、EETSSHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14PMIC N/APREPARED BYJeffery TunstallDEFENSE SUPPLY CENTER COLUMBUSSTANDARDMICROCIRCUITCHECKED BYThomas M. HessCOLUMBUS, OHIO 43216DRAWINGTHIS DRAWING IS AVAILABLEFOR USE BY ALLAPPROVED BYMonica L. PoelkingMICROCIRCUIT, DIGITAL, CMOS, IMAGE RESAMPLINGDEPARTMEN

3、TSAND AGENCIES OF THEDEPARTMENT OF DEFENSEDRAWING APPROVAL DATE92-02-12SEQUENCER, MONOLITHIC SILICONAMSC N/AREVISION LEVELBSIZEACAGE CODE672685962-89715SHEET1 OF 16DSCC FORM 2233APR 97 5962-E493-98DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited.Provided by IHSNot for

4、 ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARDMICROCIRCUIT DRAWINGSIZEA5962-89715DEFENSE SUPPLY CENTER COLUMBUSCOLUMBUS, OHIO 43216-5000REVISION LEVELBSHEET2DSCC FORM 2234APR 971. SCOPE1.1 Scope. This drawing describes device requirements for MIL-STD-883 complia

5、nt, non-JAN class level B microcircuits inaccordance with MIL-PRF-38535, appendix A.1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example:5962-89715 01 X XG01 G01 G01 G01G01 G01 G01 G01G01 G01 G01 G01G01 G01 G01 G01 Drawing number Device type Case outline Lead f

6、inish(see 1.2.1) (see 1.2.2) (see 1.2.3)1.2.1 Device type(s). The device type(s) identify the circuit function as follows:Device type Generic number Circuit function Frequency01 TMC2301 CMOS image resampling sequencer 15 MHz02 TMC2301 CMOS image resampling sequencer 18 MHz03 LF2301 CMOS image resamp

7、ling sequencer 18 MHz1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows:Outline letter Descriptive designator Terminals Package styleX CMGA3-P68 68 Pin grid array packageY CQCC2-J68 68 Square chip carrier withunformed-lead package1.2.3 Lead finish. The lead f

8、inish is as specified in MIL-PRF-38535, appendix A.1.3 Absolute maximum ratings. 1/Supply voltage range -0.5 V dc to +7 V dcDC voltage applied to outputs . -0.5 V to VDD + 0.5 V 2/Output applied voltage -0.5 V to VDD + 0.5 V 2/Output forced current -6.0 mA to +9.0 mAShort circuit duration (single ou

9、tput in high stateto ground) 1 sCase operating temperature (TC) -60G01C to +130G01CJunction temperature (TJ) . +175G01CStorage temperature range -65G01C to +150G01CLead temperature (soldering, 10 seconds) . +300G01CMaximum power dissipation (PD) 0.50 WThermal resistance, junction-to-case (G01JC) See

10、 MIL-PRF-38535_1/ Absolute maximum ratings are limiting values applied individually while all other parameters are within specified operatingconditions. Functional operation under any of these conditions is not implied.2/ Applied voltage must be current limited to specified range.Provided by IHSNot

11、for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARDMICROCIRCUIT DRAWINGSIZEA5962-89715DEFENSE SUPPLY CENTER COLUMBUSCOLUMBUS, OHIO 43216-5000REVISION LEVELBSHEET3DSCC FORM 2234APR 971.4 Recommended operating conditions.Supply voltage (VDD) . +4.5 V dc to +5.5 V dc

12、Input high voltage (VIH) . 2.0 V dc minimumInput low voltage (VIL) . 0.8 V maximumOutput high current (IOH) . -4.0 mA maximumOutput low current (IOL) . 6.0 mA maximumCase operating temperature range (TC) -55G01C to +125G01CClock pulse width low (tPWL):Device type 01 . 25 ns minimumDevice types 02 an

13、d 03 . 22 ns minimumClock pulse width high (tPWH):Device type 01 . 33 ns minimumDevice types 02 and 03 . 28 ns minimumInput setup time (tS):Device type 01 . 20 ns minimumDevice types 02 and 03 . 18 ns minimumInput hold time (tH) 2 ns minimumInput hold time, INTER 10 ns minimum2. APPLICABLE DOCUMENTS

14、2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form apart of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those listedin the issue of the Department of Defense Index of Specif

15、ications and Standards (DoDISS) and supplement thereto, cited inthe solicitation.SPECIFICATIONDEPARTMENT OF DEFENSEMIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.STANDARDSDEPARTMENT OF DEFENSEMIL-STD-883 - Test Method Standard Microcircuits.MIL-STD-973 - Configuration

16、Management.MIL-STD-1835 - Interface Standard For Microcircuit Case Outlines.HANDBOOKSDEPARTMENT OF DEFENSEMIL-HDBK-103 - List of Standard Microcircuit Drawings (SMDs).MIL-HDBK-780 - Standard Microcircuit Drawings.(Unless otherwise indicated, copies of the specification, standards, and handbooks are

17、available from the StandardizationDocument Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the textof this drawing takes precedence. Nothing in this documen

18、t, however, supersedes applicable laws and regulations unless aspecific exemption has been obtained.Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARDMICROCIRCUIT DRAWINGSIZEA5962-89715DEFENSE SUPPLY CENTER COLUMBUSCOLUMBUS, OHIO 43216-5000REVI

19、SION LEVELBSHEET4DSCC FORM 2234APR 973. REQUIREMENTS3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified ManufacturerListi

20、ng (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifyingactivity approval in accordance with MIL-PRF-38535. This QML flow

21、as documented in the Quality Management (QM) planmay make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PR

22、F-38535 is required to identify when the QML flow option is used.3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be asspecified in MIL-PRF-38535, appendix A and herein.3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.2

23、herein.3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1.3.2.3 Block diagram. The block diagram shall be as specified on figure 2.3.2.4. Image resampling geometry showing image rotation and expansion. Image resampling geometry showing imagerotation and expansion

24、shall be as specified on figure 3.3.2.5 Waveforms and test circuit. The waveforms and test circuit are as specified on figure 4.3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics areas specified in table I and shall apply over th

25、e full case operating temperature range.3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electricaltests for each subgroup are described in table I.3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part

26、 shall be marked with the PINlisted in 1.2 herein. In addition, the manufacturers PIN may also be marked as listed in MIL-HDBK-103 (see 6.6 herein). Forpackages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has theoption of not marking the “596

27、2-“ on the device.3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as anapproved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DSCC-VA prior tolisting as an approved source of supply

28、 shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535,appendix A and the requirements herein.3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided witheach lot of microcircuits delivered to this drawing.

29、3.8 Notification of change. Notification of change to DSCC-VA shall be required in accordance with MIL-PRF-38535,appendix A.3.9 Verification and review. DSCC, DSCCs agent, and the acquiring activity retain the option to review the manufacturersfacility and applicable required documentation. Offshore

30、 documentation shall be made available onshore at the option of thereviewer.Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARDMICROCIRCUIT DRAWINGSIZEA5962-89715DEFENSE SUPPLY CENTER COLUMBUSCOLUMBUS, OHIO 43216-5000REVISION LEVELBSHEET5DSCC FO

31、RM 2234APR 974. QUALITY ASSURANCE PROVISIONS4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF-38535,appendix A.4.2 Screening. Screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devicesprior to quality conf

32、ormance inspection. The following additional criteria shall apply:a. Burn-in test, method 1015 of MIL-STD-883.(1) Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revisionlevel control and shall be made available to the preparing or acquiring acti

33、vity upon request. The test circuit shallspecify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified intest method 1015 of MIL-STD-883.(2) TA = +125G01C, minimum.b. Interim and final electrical test parameters shall be as specified in table II h

34、erein, except interim electrical parametertests prior to burn-in are optional at the discretion of the manufacturer.4.3 Quality conformance inspection. Quality conformance inspection shall be in accordance with method 5005 ofMIL-STD-883 including groups A, B, C, and D inspections. The following addi

35、tional criteria shall apply.4.3.1 Group A inspection.a. Tests shall be as specified in table II herein.b. Subgroups 5 and 6 in table I, method 5005 of MIL-STD-883 shall be omitted.c. Subgroup 4 (CIN and COUT measurements) shall be measured only for the initial test and after process or designchanges

36、 which may affect input capacitance. A minimum sample size of five devices with zero rejects shall berequired.d. Subgroups 7 and 8 tests shall consist of verifying the function of the device. These tests form a part of the vendorstest tape and shall be maintained and available for review from the ap

37、proved sources of supply.4.3.2 Groups C and D inspections.a. End-point electrical parameters shall be as specified in table II herein.b. Steady-state life test conditions, method 1005 of MIL-STD-883.(1) Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under docu

38、ment revisionlevel control and shall be made available to the preparing or acquiring activity upon request. The test circuitshall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intentspecified in test method 1005 of MIL-STD-883.(2) TA = +125G01C, mi

39、nimum.(3) Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883.Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARDMICROCIRCUIT DRAWINGSIZEA5962-89715DEFENSE SUPPLY CENTER COLUMBUSCOLUMBUS, OHIO 43216-5000REVISION LEVELBS

40、HEET6DSCC FORM 2234APR 97TABLE I. Electrical performance characteristics.Test Symbol Conditions-55G01C G02 TC G02 +125G01CDevicetypeGroup AsubgroupsLimits Unit+4.5 V G02 VDD G02 +5.5 Vunless otherwise specified Min MaxHigh level output voltage VOH VDD = 4.5 V, IOH = -4 mAVIN = 2.0 V or 0.8 VAll 1, 2

41、, 3 2.4 VLow level output voltage VOL VDD = 4.5 V, IOL = 6 mAVIN = 2.0 V or 0.8 VAll 1, 2, 3 0.4 VHigh level input current IIH VDD = 5.5 VVIN = VDDAll 1, 2, 3 -10 +10 G01ALow level input current IIL VDD = 5.5 VVIN = 0.0 VAll 1, 2, 3 -10 +10 G01ASupply current IDD VDD = 5.5 VfIN = 15 MHzAll 1, 2, 3 7

42、5 mAQuiescent supply current IDDQ VDD = 5.5 V, VIN = 0.0 V 01, 02 1, 2, 3 10 mA03 5Short circuit output IOS VDD = 5.5 V 01, 02 1, 2, 3 0 -100 mAcurrent 1/ VOUT = 0.0 V03 0 -2502/High output leakagecurrentIOZH VDD = 5.5 V, VIN = VDD All 1, 2, 3 -40 +40 G01ALow output leakagecurrentIOZL VDD = 5.5 V, V

43、IN = 0.0 V All 1, 2, 3 -40 +40 G01AInput capacitance CIN See 4.3.1cfIN = 1 MHzAll 4 10 pFOutput capacitance COUT See 4.3.1cfIN = 1 MHzAll 4 10 pFFunctional test 3/ VDD = 4.5 V and 5.5 VSee 4.3.1dAll 7, 8Cycle time tCY VDD = 4.5 V 01 9, 10, 11 66 ns02, 03 10 55Output delay 3/ tD VDD = 4.5 V, CL = 20

44、pF 01, 02 9, 10, 11 35 nsSee figure 403 25Output delay, END tD(E) VDD = 4.5 V, CL = 20 pF 01, 02 9, 10, 11 45 nsSee figure 403 37See footnotes at end of table.Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARDMICROCIRCUIT DRAWINGSIZEA5962-89715

45、DEFENSE SUPPLY CENTER COLUMBUSCOLUMBUS, OHIO 43216-5000REVISION LEVELBSHEET7DSCC FORM 2234APR 97TABLE I. Electrical performance characteristics - Continued.Test Symbol Conditions-55G01C G02 TC G02 +125G01CDevicetypeGroup AsubgroupsLimits Unit+4.5 V G02 VDD G02 +5.5 Vunless otherwise specified Min Ma

46、xOutput hold time tHO VDD = 4.5 V, CL = 20 pF 01, 02 9, 10, 11 5 nsSee figure 403 2Output hold time, END tHO(E) VDD = 4.5 V, CL = 20 pF 01, 02 9, 10, 11 10 nsSee figure 403 2Three-state output tENA VDD = 4.5 V, CL = 40 pF 01, 02 9, 10, 11 35 nsenable delay 2/ 3/ See figure 403 27Three-state output t

47、DIS VDD = 4.5 V, CL = 40 pF 01, 02 9, 10, 11 35 nsdisable delay 2/ 3/ See figure 403 181/ One output to ground, 1 second duration maximum, output high.2/ Guaranteed, if not tested, to the specified limits.3/ All transitions are measured at 1.5 V level. Inputs are driven at VIL = 0.4 V and VIH = 2.4

48、V during functional testing.Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARDMICROCIRCUIT DRAWINGSIZEA5962-89715DEFENSE SUPPLY CENTER COLUMBUSCOLUMBUS, OHIO 43216-5000REVISION LEVELBSHEET8DSCC FORM 2234APR 97Case XPinnumberPin name PinnumberPin name PinnumberPin name PinnumberPin nameA2WENB9 P4 F10 GND K