DLA SMD-5962-87576 REV A-1992 MICROCIRCUITS BIPOLAR BIDIRECTIONAL I O PORT MONOLITHIC SILICON《硅单块 双向输入输出口 双极微型电路》.pdf

《DLA SMD-5962-87576 REV A-1992 MICROCIRCUITS BIPOLAR BIDIRECTIONAL I O PORT MONOLITHIC SILICON《硅单块 双向输入输出口 双极微型电路》.pdf》由会员分享，可在线阅读，更多相关《DLA SMD-5962-87576 REV A-1992 MICROCIRCUITS BIPOLAR BIDIRECTIONAL I O PORT MONOLITHIC SILICON《硅单块 双向输入输出口 双极微型电路》.pdf（17页珍藏版）》请在麦多课文档分享上搜索。

1、 - - SND-5b2-8757b REV A 9999996 0127754 279 NOTICE OF REVISION (NOR) (See MIL-STD-480 for instructions) This revision described below has been authorized for the document listed. Form Approved OM6 NO. 0704-0188 mE (-1 92/ 12/ 09 Defense Electronics Supply Center Dayton, Ohio 45444-5277 1. ACTIVITY

2、AUTHORIZED TO APPROVE CHANGE FOR GOVERNMENT 4. CAGECOOE 5. WCWENT NO. 67268 5962-87576 SIGNATURE AND TITLE DATE (YYMMDD) Monica L. Poelkinq 6. TITLE OF DOCUMENT IIICROCIRCUITS, BIPOLAR. BIDIRECTIOWAL 1/0 WRT, tHlITHIC SILIMFI 12. ACTIVITY ACCCWLISHING REVISION DESC-ECC I -7 REVISION COMPLETED (Signa

3、ture) DATE (YYMMOD) Jeffery Tunstall 92/12/09 7. REVISIoI( LETTER 8. ECP NO. I No registered users when approved. 9. COWFIGURATION ITEH (OR Sum) TO WICH E APPLIES ALL LO. DESCRIPTIOW OF REVISION Sheet 1: Revisions ltr column: add “A“ Revisions description column; add “Changes in accordance with NOR

4、5962-R040-93“. Revisions date column: add “92-12-09“. Revision level block: add “A“. Revision status of sheet: for sheet 1 MCLK = High 31 YV data propagation delay ltpD4 I MCLK = WC = Ur = High; 31 - To to UD data clock delay ItpD5 1 wc = uf(: = High; -v = Stable - 3/ + MCLK to UD Output enable timi

5、ng: I I I I UD output enable c UOC to UD UIC = High - 3/ I I l l UD input recovery + UTC to UD %E2 lJU = Low - 31 I I II TV data master enable +mtofV TV data read enable cRCtofV TV data write recovery lQE5 i Kc = = LOW - 31 4 wc to Tv I I I Output disable timing: I l I I UD output disable .f OT to U

6、D 1 IT = High - 31 1 I I UD input override 4 C to (tDD2 I lJ = LOU - 3/ I I l I I I I 3/ 41 - IV data master disable (kD3 I wc = Rc = LOW - +TolE:toTV III 9,10,11 I I 451 ns III 1- I I 551 ns III 17 I I 551 ns III I11 I I 451 ns III III 1 I 551 ns III I I III Ill III I III III I I 451 ns I I 451 ns

7、I i I 451 i 45) ns I 1 451 ns I I 401 ns I I 451 ns III III III III III I I 401 ns III 1 1 401 ns III I I 401 ns III See footnotes at end of table. 5962-87576 MILITARY DRAWING DEFENSE ELECTRONICS SUPPLY CENTER REVISION LEVEL ir U S GOVERNMENT PRINTING OFFICE 1987-549Q96 DESC FORM 193A SEP 87 License

8、d by Information Handling ServicesSMD-59b2-7576 REV A 999999b OL277b0 572 TABLE I. Electrical performance characteristics - Continued. Test etup time: UD clock setup time UD to J. MCLK UD setup time UD to 4 UIC User input control setup time + UT(: to + MCLK TV data setup time TV to + MCLK TV master

9、enable setup time + TiE to + MCLK TV write control setup time 4 WC to + MCLK io1 d times : UD clock hold time J. MCLK to UD UD control hold time 4 UT(: to UD User input control hold time J. MCLK to 4 Tm: Tv data hold time J. MCLK to TV TV master enable hold time + MCLK to 4 Fi 1v write control hold

10、time f MCLK to + WC I Condi ti ons I Symbol I -55OC TC 5 +125OC 1Group A I I unless othrwise-specified subgroups I I I I 1 I tS2 I MCLK = High 31 I I -1 I 4.5 v vc 5.5 v I = l I t4 1 WC = T = High; RE = Low 31 I I I I 51 I I t5 I WC = UTC = High Y I I I I I I tH2 I MCLK = High Y I tH5 i FE = = High

11、31 I 9,10,11 I -1 I Limits I 1 Unit TliKZl II T II II 151 I ns li II 251 I ns 251 I ns 151 I ns 201 I ns II II II II II II 401 I ns II I II II II 201 1 ns loi i ns II II II II I I 51 I ns LO I I ns oi i ns II II 01 i ns II I The input current includes the three-state leakage current of the output dr

12、iver on the data lines 1 Only one output may be shorted at a time. 1 Test loading circuit and timing diagrams see figures 4 and 5. 1 These parameters are measured with a capacitive loading of 50 pf and represent the output driver turn-off time. / If edge of MCLK to avoid unintended writing into or s

13、election of the 1/0 port. is to be high (inactive), it must be setup before the rising edge and held after the fallin SIZE 5962-87576 STANDARDIZED MILITARY DRAWING A REVISION LEVEL SHEET 6 DEFENSE ELECTRONICS SUPPLY CENTER MlN. OHIO 45444 r I I I u s QOVERNYENT PRWTING ORCE mn7-5194 DESC FORM 193A S

14、EP a7 I . . Licensed by Information Handling Servicest SMD-59b2-8757b REV A m 999999b 0127761 409 m I UD5 3 I UD4 4 21 IV5 I I b MCLK I I I I l l I TOP VIEW Pin. iio. Ideticifier FLinctiJii I-d 9 10 Il 12 13 i.( 13 LU-3 24 Tiired-sLdie bidireccidndlser ddcd JJJ uus. UJJ corresporidz to IVJ. Uher iii

15、puc coiitrJI-dctiw luhi iiipuc tu enale datd inpuc froin UUO-U7. Mast= enaule-dctive lov input CO enasle tlie IV ULIS for ddtd input or ddtd oucput, UD-bus operation5 are unaffected. Ground Master cloc x-dc ti ve ni yii i npdt ( f roiil microcoiitrJiler/ dseJ to st-oe ddtd into data latches froin ti

16、t it aiid Ud buses. tledd coiiitri, I -dcLi-xeC FORM 193A SEP 87 Licensed by Information Handling Services _ SMD-5762-87576 REV A m 9999996 0327762 345 m - , Functional operat ion UD bus control The user data (UD) busnterf- is controlled by the UIC and UDC inputs. .Data input to the UD bus is synchr

17、onous with MCLK, that is, with UIC low, information is writ- ten into the data latches only when MCLK is high. Output drivers on the UD busare enabled when is low and UIC is high. Input/output control of UD Bus UIC a MCLK function.of UD bus , , H L X output L X H Input data L X L inactive H H X inac

18、tive X = dont care Bus logic level Data written into the I/D port from either bus will appear inverted when read from the other bus. Data written into either bus will not be inverted when read from the same bus. (Note. A logfc I 1“ to a high level on the UD bus even though the bus is inverted). The

19、device wakes up in the unselected state with all data bits latched at the “logic 1“ level (UD bus outputs high if enabled). in microcontroller software corresponds Input/output control of TV bus II II J FIGURE 2. Truth tables. TV bus control Input/output control of the bus is shown-above.Jhis bus is

20、 control- 13d by RC, WC, ME, and MCLK. The IV bus is enabled for output (micro- ontroller read operation) when FI, RC, and WC are all low. Data is written into thedata latches from the IV bus when ME is low and both WC and MCLK are high. To avoid datadnput conflicts, inputs fina the IV bus are inhib

21、ited when UIC is low; under all other conditions, the fv and UD busses operate inde- pendently. The microcontroller left bank (LB) and rightJank (RE) outputs can control the ME inputs for two banks of I/O devices, thus acting as a ninth address bit. If more than one I/O port are tobe connected to th

22、e same bank (LE or KB) of the microcontroller, se- lection of each device must be accomplished with external control logic to avoid bus conflicts. STDARIZED SIZE A 5962-87576 I MILSTAR11 DRAWING DEFENCE ELECTRONICS SUPPLY CENTER RMCK)N LNU SHEET I MYlON, OHK) 45449 8 I? U S GOVERNMENT PRWllNG OFFICE

23、 i887 -5494% ESC FORM 193A SEP a7 Licensed by Information Handling ServicesSMD-59b2-87576 REV A m 9b 0227763 281 STANDARDIZED SIZE A MILITARY DRAWING - IV x 5 96 2 - 8 7 5 7 6 MCLK 7 1 I OF e BIT SLICES I I - I I - - I QT- “OC IV WRITE , t 1 I 1 I I wc ME 1 FIGUKE 3. Logic diagram. I I I $i U S GOVE

24、RNMENT PRINTING OFFICE 1987-549.090 DESC FORM 193A SEP a7 Licensed by Information Handling ServicesSMD-59b2-87576 REV A 999999b OL277b4 118 O ITPI - IV flus +5V o 232 a T UNDER lEST OTT 300Pf* - OUTPUT UND.ER TE ST UD BUS OTT 100pf * * Total equivalent load= fixed capacitance and test circuit capaci

25、tance. FIGURE 4. Test loading circuits. SIZE 5962-87576 STANDARDIZED IVULITAW EWIALWdNG A DMNSE ELECTRONICS SUPPLY CENTER RMcK)NLEyEL SHEET i mmN, oHIO4S444 10 US GOMRNMENTPRHTINGORICE 1987-549096 QESC FRM 193A SEP 87 Licensed by Information Handling ServicesSMD-59b2-8757b REV A - - b O327765 054 =

26、MCLK OD (INPUT FROM USER SYSTEM) - IV (OUTPUT TO MICROPROCESSOR) LEGEND: STATIC CONETIONS: - SC = WC = ME= Low; UOC = High = TllREE- STATE a. User data input tiining v/A, = CIiANGING DATA NOTES : 1. The actual time for stable data on the fi bus is the latest propagation from tPD1, tPD2. tPD3. 2. 3.

27、The UD input must satisfy the setup-time requirements for both ts1 and ts2. Minimum hold-time required for the UD input is the earlier of the times specified by tH1 and tH2. FIGURE 5. Timing diagrams. STANDARDIZED SIZE A 5962-87576 MILITARY DRAWING hall be made available onshore at the option of the

28、 reviewer. DESC, DESCs agent, and the acquiring activity retain the option to 4. QUALITY ASSURANCE PROVISIONS 4.1 Sampling and inspection. 4.2 Screening. Screening shall be in accordance with method 5004 of MIL-STD-883, and shall be Sampling and inspection procedures shall be in accordance with ;ect

29、ion 4 of MIL-M-38510 to the extent specified in MIL-STD-883 (see 3.1 herein). :onducted on all devices prior to quality conformance inspection. ;hall apply: a. Burn-in test, method 1015 of MIL-STD-883. (1) (2) TA = +125OC, minimum. Interim and final electrical test parameters shall be as specified i

30、n table II herein, except interim electrical parameter tests prior to burn-in are optional at the discretion of the manufacturer. 4.3 Quality conformance inspection. Quality conformance inspection shall be in accordance with The following additional criteria Test condition A, B, C, or D using the ci

31、rcuit submitted with the certificate of compliance (see 3.5 herein). b. iethod %OS of MIL - STD 883 including groups A, B, C, and D inspections. :riteria shall apply. The following additional SHEET 14 4.3.1 a. b. C. 4.3.2 a. h. Group A inspection. Tests shall be as specified in table II herein. Subg

32、roups 4, 5, and 6 in table I, method 5005 of MIL-STD-883 shall be omitted. Subgroups 7 and 8 tests sufficient to verify the truth tables. Groups C and D inspections. End-point electrical parameters shall be as specified in table II herein. Steady-state life test conditions, method 1005 of MIL-STD-88

33、3. (1) Test condition A, B, Cy or D using the circuit submitted with the certificate of compliance (see 3.5 herein). (2) TA = +125OC, minimum. (3) Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STO-883. Licensed by Information Handling ServicesSMD-5362-87576 REV A 999999b 0127

34、769 7TT I TABLE II. Electrical test requirements. 1 I I I MIL-STD-883 test requirements I Subgroups I I I (per method 1 I I 5005, table I) I I 1 I I I interim electrical parameters I I I I (method 5004) I I I 7, IFinal electrical test parameters1 1*,2,3,7,9 I I (method 5004) I I l l I I I 1,2,3,7,8,

35、9, I IGroup A test requirements I (method 5005) l 10,11 I - I I I IGroups C and D end-point I 1,2,3 l I electrical parameters l I I (method 5005) I I * PDA applies to subgroup 1. I 5. PACKAGING 5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-M-38510. I I 6.

36、 NOTES 6.1 Intended use. Microcircuits conforming to this drawing are intended for use when military specifi-ot exist and qualified military devices that will perform the required function are not available for OEM application. by this drawing has been qualified for listing on QPL-38510, the device

37、specified herein will be inactivated and will not be used for new design. for al 1 applications. covered by a contractor-prepared specification or drawing. When a military specification exists and the product covered The QPL-38510 product shall be the preferred item 6.2 Replaceability. Microcircuits

38、 covered by this drawing will replace the same generic device fi u S GOVERNMENT PRINTING OFFICE 1987-5494196 DESC FORM 193A SEP ai Licensed by Information Handling ServicesSMD-5962-87576 REV A m 999999b O127770 411 m 6.4 Approved soume of supply. An approved source of supply is listed herein. Additi

39、onal cources will be added as.they become available. The vendor listed herein has agreed to this drawing and a certificate of compliance (see 3.5 herein) has been submitted to DESC-ECS. 1 IYendor I Vendor I Rep1 acement I I part number Inumber I number L/ I part number I I Military drawing ICAGE I s

40、imilar part Imilitary specification1 I I I I I I I I I I I 5962-8757601XX I 18324 I 8X371/BXA I I I I I I I I I l I - i/ Caution. Do not use this number for item acquisition. Items - acquired to this number may not satisfy the performance require- ments of this drawing. Vendor CAGE number 18324 Vend

41、or name and tddress Signetics Coi-poration 4130 South Market Court Sacramento, CA 95834 - SIZE 5962-87576 STANDARDIZED MILITARY DRAWING A I DEFENSE ELECTRONICS SUPPLY CEMER DAYION, OHIO 45444 1 FEvtcloN LEVEL I I U S WVERNYENT PRINTING OFFICE 1987-549696 ESC FORM 193A SEP 87 7 Licensed by Information Handling Services