DLA DSCC-VID-V62 09644 REV A-2009 MICROCIRCUIT LINEAR 5 A HIGH OUTPUT CURRENT PULSE WIDTH MODULATION CONVERTER MONOLITHIC SILICON.pdf

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1、 REVISIONSLTR DESCRIPTION DATE APPROVEDPrepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV PAGE 1 2 3 4 5 6 7 8 9 10 11 PMIC N/A PREPARED BY RICK OFFICER DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 Original date of drawing YY-MM-DD CHECK

2、ED BY RAJESH PITHADIA TITLE MICROCIRCUIT, LINEAR, 5 A, HIGH OUTPUT CURRENT PULSE WIDTH MODULATION CONVERTER, MONOLITHIC SILICON 09-08-18 APPROVED BY CHARLES F. SAFFLE SIZE A CODE IDENT. NO. 16236 DWG NO. V62/09644 REV PAGE 1 OF 11 AMSC N/A 5962-V077-09 Provided by IHSNot for ResaleNo reproduction or

3、 networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09644 REV PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a 5 A, high output current pulse width modulation converter microcircuit,

4、with an operating temperature range of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/09644

5、- 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 TPS5450-EP 5 A, high output current pulse width modulation converter 1.2.2 Case outline(s). The case outline(s) are as specified herein. Outl

6、ine letter Number of pins JEDEC PUB 95 Package style X 8 See figure 1 Plastic surface mount 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacture: Finish designator Material A Hot solder dip B Tin-lead plateC Gold plateD PalladiumE

7、 Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09644 REV PAGE 3 1.3 Absolute maximum ratings. 1/ 2/ Input voltage range (VIN): VINpi

8、n -0.3 V to 40 V 3/ BOOT pin . -0.3 V to 50 V PH pin (steady state) -0.6 V to 40 V 3/ ENA pin -0.3 V to 7 V BOOT-PH pin . 10 V VSENSE pin . -0.3 V to 3 V PH pin (transient 10 ns) -1.2 V Source current (IO) (PH pin) . Internally limited Leakage current (IILK) (PH pin) 10 A Operating virtual junction

9、temperature range . -55C to +150C Storage temperature range -65C to +150C 1.4 Recommended operating conditions. 4/ Input voltage range (VIN) . 5.5 V to 36 V Operating junction temperature range (TJ) -55C to +125C 1.5 Dissipation ratings table. 5/ 6/ Package Thermal impedance junction to ambient 4 la

10、yer board with solder 7/ 30C/W 1/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditio

11、ns” is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. 2/ All voltages are within respect to network ground terminal. 3/ Approaching the absolute maximum rating for the VINpin may cause the voltage on the PH pin to exceed the absolute ma

12、ximum rating. 4/ Use of this product beyond the manufacturers design rules or stated parameters is done at the users risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. 5/ Maximum power dissipation may be limited by overcurrent

13、 protection. 6/ Power rating at a specific ambient temperature TAshould be determined with a junction temperature of 125C. This is the point where distortion starts to substantially increase. Thermal management of the final printed circuit board (PCB) should strive to keep the junction temperature a

14、t or below 125C for performance and long term reliability. See thermal calculations in the application section of the manufacturers datasheet for more information. 7/ Test board conditions: 2 inch x 1.85 inch, four layers, 0.062 inch (1.57 mm) thickness. 2 ounce copper traces located on the top and

15、bottom of the PCB. 2 ounce copper ground planes on the two internal layers. Four thermal vias in the thermal pad area under the device package. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE

16、 IDENT NO. 16236 DWG NO. V62/09644 REV PAGE 4 2. APPLICABLE DOCUMENTS JEDEC PUB 95 Registered and Standard Outlines for Semiconductor Devices (Applications for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or online at http:/www.jed

17、ec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be

18、 marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physica

19、l dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Block diagram. The block diagr

20、am shall be as shown in figure 3. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09644 REV PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol

21、Conditions VIN= 5.5 V to 36 V unless otherwise specifiedTemperature, TJDevice type Limits Unit Min Max Supply voltage (VINpin) section Quiescent current IQVSENSE = 2 V, not switching, PH pin open -55C to +125C 01 4.4 mA Shutdown, ENA = 0 V 60 A Undervoltage lockout (UVLO) section Start threshold vol

22、tage, UVLO VTH-55C to +125C 01 5.3 typical V Hysteresis voltage, UVLO VHYS-55C to +125C 01 330 typical mV Voltage reference section Voltage reference accuracy VRA25C 01 1.202 1.239 V IO= 0 A to 5 A -55C to +125C 1.193 1.245 Oscillator section Internally set free running frequency fISFR+25C 01 400 60

23、0 kHz -55C to +125C 375 600 Minimum controllable on time tcmin-55C to +125C 01 220 ns Maximum duty cycle DCMAX-55C to +125C 01 87 % Enable (ENA pin) section Start threshold voltage, ENA VSTART-55C to +125C 01 1.3 V Stop threshold voltage, ENA VSTOP-55C to +125C 01 0.5 V Hysteresis voltage, ENA VHYS-

24、55C to +125C 01 450 typical mV Internal slow start time tISS(0 100%) -55C to +125C 01 5.4 10 ms See footnote at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 D

25、WG NO. V62/09644 REV PAGE 6 TABLE I. Electrical performance characteristics Continued. 1/ Test Symbol Conditions VIN= 5.5 V to 36 V unless otherwise specifiedTemperature, TJDevice type Limits Unit Min Max Current limit section Current limit IL+25C 01 6.0 9.0 A -55C to +125C 4.4 11.7 Current limit hi

26、ccup time tCL+25C 01 13 20 ms -55C to +125C 13 22.5 Thermal shutdown section Thermal shutdown trip point TTSTP-55C to +125C 01 135 C Thermal shutdown hysteresis TTSH-55C to +125C 01 14 typical C Output MOSFET section High side power MOSFET switch rDS(on)VIN= 5.5 V -55C to +125C 01 150 typical m 110

27、typical 1/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence

28、 of specific parametric testing, product performance is assured by characterization and/or design. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09644 REV PAGE 7

29、 Case X FIGURE 1. Case outline. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09644 REV PAGE 8 Case X continued. Symbol Dimensions Inches Millimeters Min Max Min

30、 Max A 0.055 0.061 1.40 1.55 A1 0.00 0.005 0.00 0.13 A2 - 0.066 - 1.68 b 0.013 0.019 0.35 0.49 c 0.007 nominal 0.20 nominal D 0.188 0.196 4.80 4.98 E 0.149 0.157 3.81 3.99 E1 0.229 0.244 5.84 6.20 e 0.049 BSC 1.27 BSC L 0.016 0.035 0.41 0.89 n 8 8 NOTES: 1. Controlling dimensions are millimeter, inc

31、h dimensions are given for reference only. 2. Body dimensions do not include mold flash or protrusion not to exceed 0.15 mm (0.006 inch). 3. This package is designed to be soldered to a thermal pad on the board. Refer to technical brief, power pad thermally enhanced package, manufacturers literature

32、 number SLMA002 for information regarding recommended board layout. A copy of the manufacturers datasheet is available at . FIGURE 1. Case outline continued. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OH

33、IO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09644 REV PAGE 9 Device type 01 Case outline X Terminal number Terminal symbol Description 1 BOOT Boost capacitor for the high side field effect transistor (FET) gate driver. Connect 0.01 F low equivalent series resistance (ESR) capacitor from BOOT pin to P

34、H pin. 2 NC Not internal connection. 3 NC Not internal connection. 4 VSENSE Feedback voltage for the regulator. Connect to output voltage divider. 5 ENA On/off control. Below 0.5 V, the device stops switching. Float the pin to enable. 6 GND Ground. Connect to thermal pad. 7 VINInput supply voltage.

35、Bypass VINpin to GND pin close to device package with a high quality low ESR ceramic capacitor. 8 PH Source of the high side power metal oxide semiconductor field effect transistor (MOSFET). Connected to external inductor and diode. 9 POWER PAD GND pin must be connected to the exposed pad for proper

36、 operation. FIGURE 2. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09644 REV PAGE 10 FIGURE 3. Block diagram. Provided by IHSNot for Resal

37、eNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09644 REV PAGE 11 4. VERIFICATION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test re

38、quirements as indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPARATION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeli

39、ng, and marking shall be in accordance with the manufacturers standard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein

40、 is based on the salient characteristics of the device manufacturers data book. The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply her

41、ein is not to be construed as a guarantee of present or continued availability as a source of supply for the item. Vendor item drawing administrative control number 1/ 2/ Device manufacturer CAGE code Top side marking Package 3/ Vendor part number V62/09644-01XE 01295 5450EP Thermally enhanced Reel

42、of 2500 TPS5450MDDAREP 1/ The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation. 2/ For the most current package and ordering information, see the package option addendum at the end of the manufacturers data sheet , or use webs

43、ite . 3/ Package drawings, thermal data, and symbolization are available at CAGE code Source of supply 01295 Texas Instruments, Inc. Semiconductor Group8505 Forest Lane P.O. Box 660199 Dallas, TX 75243 Point of contact: U.S. Highway 75 South P.O. Box 84, M/S 853 Sherman, TX 75090-9493 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-