DLA DSCC-VID-V62 09640 REV A-2011 MICROCIRCUIT LINEAR ULTRALOW POWER VOLTAGE COMPARATOR MONOLITHIC SILICON.pdf
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1、 REVISIONSLTR DESCRIPTION DATE APPROVEDPrepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PMIC N/A PREPARED BY RICK OFFICER DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 Original date of drawing YY-MM-DD CH
2、ECKED BY RAJESH PITHADIA TITLE MICROCIRCUIT, LINEAR, ULTRALOW POWER, VOLTAGE COMPARATOR, MONOLITHIC SILICON 11-06-28 APPROVED BY CHARLES F. SAFFLE SIZE A CODE IDENT. NO. 16236 DWG NO. V62/09640 REV PAGE 1 OF 15 AMSC N/A 5962-V045-11 Provided by IHSNot for ResaleNo reproduction or networking permitte
3、d without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09640 REV PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a ultralow power, voltage comparator microcircuit, with an operating temperature range of -55C to +125C.
4、 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/09640 - 01 X B Drawing Device type Case outline Lead finish
5、 number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 MAX921 Single, micropower, voltage comparator with internal hysteresis and 1 % precision reference 02 MAX922 Dual, micropower, voltage comparator 03 MAX923 Dual, micropower, voltage comparator w
6、ith internal hysteresis and 1 % precision reference 04 MAX924 Quad, micropower, voltage comparator 1.2.2 Case outline(s). The case outline(s) are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 8 MS-012-AA Small outline Y 16 MS-012-AC Small outline1.2.3 Lead finishes.
7、 The lead finishes are as specified below or other lead finishes as provided by the device manufacture: Finish designator Material A Hot solder dip B Tin-lead plateC Gold plateD PalladiumE Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without licen
8、se from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09640 REV PAGE 3 1.3 Absolute maximum ratings. 1/ +V to V, +V to GND, GND to -V . -0.3 V +12 V Inputs: Current, +IN_, -IN_, HYST . 20 mA Voltage, +IN_, -IN_, HYST . (+V + 0.3 V) to (-V 0.3 V) Outputs: Curren
9、t, REF 20 mA Current, OUT_ 50 mA Voltage, REF (+V + 0.3 V) to (-V 0.3 V) Voltage, OUT_ : Device types 01, 04 (+V + 0.3 V) to (GND 0.3 V) Device types 02, 03 (+V + 0.3 V) to (-V 0.3 V) OUT_ short-circuit duration (+V 5.5 V) Continuous Junction temperature range (TJ) +150C Storage temperature range (T
10、STG) -65C to +150C Lead temperature (soldering, 10 seconds) . +300C Electrostatic discharge (ESD): Human body model (HBM) . 2,500 V Moisture sensitivity level (MSL) Level 1 1.4 Recommended operating conditions. 2/ Operating free-air temperature range (TA) . -55C to +125C 1.5 Thermal data table. Case
11、 outlines X X Y Y Unit PC board Single layer Multi-layer 3/ Single layer Multi-layer 3/ Power dissipation (PD) maximum at 70C 471 606 696 1067 mW PDderating above +70C 5.9 7.6 8.7 13.3 mW/C Thermal resistance, junction to case (JC) 40 38 32 24 C/W Thermal resistance, junction to ambient (JA) 170 132
12、 115 75 C/W 1/ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied
13、. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ Use of this product beyond the manufacturers design rules or stated parameters is done at the users risk. The manufacturer and/or distributor maintain no responsibility or liability for product use
14、d beyond the stated limits. 3/ Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maxim- Provided by IHSNot for ResaleNo reproduction or networking pe
15、rmitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09640 REV PAGE 4 2. APPLICABLE DOCUMENTS JEDEC PUB 95 Registered and Standard Outlines for Semiconductor Devices JEDEC JESD51-7 High Effective Thermal Conductivity Test Board for Leaded
16、Surface Mount Packages (Applications for copies should be addressed to the JEDEC Office, 3103 North 10th Street, Suite 240-S, Arlington, VA 22201-2107 or online at http:/www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as sh
17、own in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. Th
18、e maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outlines.
19、The case outlines shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO.
20、16236 DWG NO. V62/09640 REV PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions +V = 5 V, -V = GND unless otherwise specifiedTemperature, TA Device type Limits Unit Min Max Power requirements Supply voltage range 2/ -55C to +125C All 2.5 11 V Supply current +IN = -IN +
21、100 mV, HYST = REF +25C 01 3.2 A -55C to +125C 5 +IN = -IN + 100 mV +25C 02 3.2 -55C to +125C 5 +IN = -IN + 100 mV, HYST = REF +25C 03 4.5 -55C to +125C 7.5 +IN = -IN + 100 mV +25C 04 6.5 -55C to +125C 11 Comparator section Input offset voltage VOSVCM= 2.5 V -55C to +125C All 10 V Input leakage curr
22、ent (-IN, +IN) IINL+IN = -IN = 2.5 V -55C to +125C All 40 nA Input leakage current (HYST) IINL-55C to +125C 01,03 0.02 typical nA Input common mode voltage range -55C to +125C All -V +V 1.3 V Common mode rejection ratio CMRR -V to (+V 1.3) -55C to +125C All 1.0 mV/V Power supply rejection ratio PSRR
23、 +V = 2.5 V to 11 V -55C to +125C All 1.0 mV/V Voltage noise 100 Hz to 100 kHz -55C to +125C All 20 typical VRMSHysteresis input voltage range -55C to +125C 01,03 REF 0.05 V REF V Response time Overdrive = 10 mV, 100 pF load +25C All 12 typical s Overdrive = 100 mV, 100 pF load 4 typical See footnot
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