DLA DSCC-VID-V62 09639-2011 MICROCIRCUIT LINEAR QUAD 1 2 MUE A SINGLE SUPPLY OPERATIONAL AMPLIFIER MONOLITHIC SILICON.pdf
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1、 REVISIONSLTR DESCRIPTION DATE APPROVEDPrepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV PAGE 1 2 3 4 5 6 7 8 9 10 PMIC N/A PREPARED BY RICK OFFICER DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 Original date of drawing YY-MM-DD CHECKED BY RAJESH
2、 PITHADIA TITLE MICROCIRCUIT, LINEAR, QUAD, 1.2 A, SINGLE SUPPLY OPERATIONAL AMPLIFIER, MONOLITHIC SILICON 11-07-07 APPROVED BY CHARLES F. SAFFLE SIZE A CODE IDENT. NO. 16236 DWG NO. V62/09639 REV PAGE 1 OF 10 AMSC N/A 5962-V052-11 Provided by IHSNot for ResaleNo reproduction or networking permitted
3、 without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09639 REV PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a quad, 1.2 A, single supply operational amplifier microcircuit, with an operating temperature range of -
4、55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/09639 - 01 X B Drawing Device type Case outlin
5、e Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 MAX418 Quad, 1.2 A, single supply operational amplifier 1.2.2 Case outline(s). The case outline(s) are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style
6、X 14 MS-012-AB Small outline1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacture: Finish designator Material A Hot solder dip B Tin-lead plateC Gold plateD PalladiumE Gold flash palladium Z Other Provided by IHSNot for ResaleNo re
7、production or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09639 REV PAGE 3 1.3 Absolute maximum ratings. 1/ 2/ Total supply voltage (+V to -V) . 12 V Input voltage (+V + 0.3 V) to (-V 0.3 V) Continuous current: All in
8、put pins . 10 mA All other pins 50 mA Short-circuit duration Continuous Junction temperature (TJ) 150C Storage temperature range (TSTG) . -65C to +160C Lead temperature (soldering, 10 seconds) . +300C Electrostatic discharge (ESD): Human body model (HBM) . 2,000 V Moisture sensitivity level (MSL) Le
9、vel 1 1.4 Recommended operating conditions. 3/ Supply voltage +V = +2.5 V, -V = -2.5 V Operating free-air temperature range (TA) . -55C to +125C 1.5 Thermal data table. Case outline letter X X Units PC board Single layer Multi-layer 4/ Power dissipation (PD), maximum at +70C 667 988 mW Power dissipa
10、tion (PD) derating above +70C 8.3 12.3 mW/C Thermal resistance, junction to case (JC) 37 32C/W Thermal resistance, junction to ambient (JA) 120 81 C/W 1/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and function
11、al operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ The absolute maximum ratings do not apply to devices suppli
12、ed in die or wafer form. 3/ Use of this product beyond the manufacturers design rules or stated parameters is done at the users risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. 4/ Package thermal resistances were obtained us
13、ing the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maxim- Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO S
14、IZE A CODE IDENT NO. 16236 DWG NO. V62/09639 REV PAGE 4 2. APPLICABLE DOCUMENTS JEDEC PUB 95 Registered and Standard Outlines for Semiconductor Devices JEDEC JESD51-7 High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages (Applications for copies should be addressed to the
15、Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or online at http:/www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or
16、logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performan
17、ce characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal
18、 connections. The terminal connections shall be as shown in figure 2. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09639 REV PAGE 5 TABLE I. Electrical performance charac
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