DLA DSCC-VID-V62 05613 REV B-2012 MICROCIRCUIT DIGITAL CMOS 14-BIT 125 MSPS ANALOG-TO-DIGITAL CONVERTER MONOLITHIC SILICON.pdf

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1、 REVISIONS LTR DESCRIPTION DATE APPROVED A Add device type 02. Update boilerplate to current revision. - CFS 06-12-15 Thomas M. Hess B Update boilerplate paragraphs to current requirements. - PHN 12-02-14 Thomas M. Hess CURRENT DESIGN ACTIVITY CAGE CODE 16236 HAS CHANGED NAMES TO: DLA LAND AND MARIT

2、IME COLUMBUS, OHIO 43218-3990 Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV B B B B B B B B B B B B B B PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Charles F. Saffle DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO 43218-3990 Origi

3、nal date of drawing CHECKED BY Charles F. Saffle TITLE MICROCIRCUIT, DIGITAL, CMOS, 14-BIT, 125 MSPS ANALOG-TO-DIGITAL CONVERTER, MONOLITHIC SILICON YY-MM-DD 05-08-15 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/05613 REV B PAGE 1 OF 14 AMSC N/A 5962-V032-12 Provided by IHSNot

4、 for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/05613 REV A PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance 14-bit, 125 MSPS Analog-

5、to-Digital Converter microcircuit, with an operating temperature range of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the en

6、gineering documentation: V62/05613 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device types. Device type Generic Circuit function 01 ADS5500-EP 14-bit, 125 MSPS Analog-to-Digital Converter 02 ADS5500-EP 14-bit, 125 MSPS Analog-to-Digital Con

7、verter 1.2.2 Case outlines. The case outlines are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 64 JEDEC MS-026 Plastic Quad Flatpack 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish

8、designator Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/05613

9、 REV A PAGE 3 1.3 Absolute maximum ratings. 1/ 2/ Supply voltage range: AVDDto AGND. -0.3 V to +3.7 V DRVDDto DRGND-0.3 V to +3.7 V Supply voltage range: AGNDto DRGND. -0.1 V to +0.1 V Analog input to AGND. -0.15 V to +2.5 V Logic input to DRGND. -0.3 V to DRVDD+ 0.3 V Digital data output to DRGND-0

10、.3 V to DRVDD+ 0.3 V Input current (any input) 30 mA Operating temperature range -55C to +125C Junction temperature +142C Storage temperature range (TSTG) . -65C to +150C Package Thermal Characteristics: Thermal resistance, junction to ambient (RTJA): 3/ 4/ Same package form without bond pad 75.83C/

11、W Bond pad not connected to PCB Thermal plane . 42.2C/W Bond pad connected to PCB thermal plane 21.47C/W Thermal resistance, junction to case (RTJC): 3/ 4/ Same package form without bond pad 7.8C/W Bond pad not connected to PCB Thermal plane . 0.38C/W Bond pad connected to PCB thermal plane 0.38C/W

12、1.4 Recommended operating conditions. Supplies: Supply voltage range: Analog supply voltage (AVDD) . +3.0 V to +3.6 V Output driver supply voltage (DRVDD) . +3.0 V to +3.6 V Analog Input: Differential input range (typical). 2.3 VPPInput common-mode voltage (VCM) . +1.5 V to +1.6 V 5/ Digital output:

13、 Maximum output load (typical) 10 pF Clock Input: ADCLK input sample rate (sine wave) (1/tC): DLL On 60 MSPS to 125 MSPS DLL Off 10 MSPS to 80 MSPS Clock amplitude, sine wave, differential (typical) . 3 VPPClock duty cycle (typical) . 50% Open free-air temperature range . -55C to +125C _ 1/ Stresses

14、 beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-

15、maximum-rated conditions for extended periods may affect device reliability. 2/ Over operating free-air temperature range unless otherwise specified. 3/ Specified with the bond pad on the backside of the package soldered to a 2-oz Cu plate PCB thermal plane. 4/ Airflow is at 0 LFM (no airflow). 5/ I

16、nput common-mode should be connected to CM. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/05613 REV A PAGE 4 2. APPLICABLE DOCUMENTS JEDEC SOLID STATE TECHNOLOGY

17、 ASSOCIATION (JEDEC) JEDEC PUB 95 Registered and Standard Outlines for Semiconductor Devices Copies of these documents are available online at http:/www.jedec.org or from JEDEC Solid State Technology Association, 3103 North 10th Street, Suite 240S, Arlington, VA 22201.) 3. REQUIREMENTS 3.1 Marking.

18、Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part n

19、umber and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction

20、, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outlines. The case outlines shall be as shown in 1.2.2 and figure 1. 3.5.2 Block diagram. The block diagram shall be as shown in figure 2. 3.5.3 Terminal connections. The terminal connections shall be as shown in figure 3. 3

21、.5.4 Timing waveforms. The timing waveforms shall be as shown in figures 4a 4b. 3.5.5 Terminal functions. The terminal functions shall be as shown in figure 5. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS,

22、OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/05613 REV A PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol Test conditions unless otherwise specified Device type Limits Unit Min Typ Max ELECTRICAL CHARATERISTICS 2/ Resolution All 14 Tested Bits Analog inputs Differential input r

23、ange All 2.3 VPPDifferential input impedance 6.6 k Differential input capacitance 4 pF Total analog input common-mode current 4 3/ mA Analog input bandwidth Source impedance = 50 750 MHz Conversion Characteristics Maximum sample rate All 4/ 125 MSPS Data latency See figure 4a. 16.5 Clock cycles Inte

24、rnal Reference Voltages Reference bottom voltage VREFMAll 0.97 V Reference top voltage VREFP2.11 V Reference error 25C -4 +4 % -55C to +125C -5 +5 Common-mode voltage output VCM1.55 0.05 V Dynamic DC Characteristics and Accuracy No missing codes All Tested Differential linearity error DNL fIN= 10 MH

25、z -0.9 0.75 +1.1 LSB Integral linearity error INL fIN= 10 MHz 25C -5 +5 LSB -55C to +125C -8 +8 Offset error 1.5 mV Offset temperature coefficient 0.0007 %/C Gain error 0.45 %FS Gain temperature coefficient 0.01 %/C Dynamic AC Characteristics Signal-to-noise ratio SNR fIN= 10 MHz 25C All 70.5 71.5 d

26、BFS -55C to +125C 68 71.5 fIN= 30 MHz 71.5 fIN= 55 MHz 71.5 fIN= 70 MHz 25C 70 71.2 -55C to +125C 66.5 71 fIN= 100 MHz 70.5 fIN= 150 MHz 70.1 fIN= 225 MHz 69.1 RMS output noise Input tied to common-mode 1.1 LSB See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking

27、 permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/05613 REV A PAGE 6 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Test conditions unless otherwise specified Device type Limits Unit Min Typ Max

28、 ELECTRICAL CHARATERISTICS - Continued. 2/ Dynamic AC Characteristics - Continued. Spurious-free dynamic range SFDR fIN= 10 MHz 25C All 82 84 dBc -55C to +125C 76 84 fIN= 30 MHz 84 fIN= 55 MHz 79 fIN= 70 MHz 25C 80 83 -55C to +125C 75 82 fIN= 100 MHz 82 fIN= 150 MHz 78 fIN= 225 MHz 74 Second-harmoni

29、c HD2 fIN= 10 MHz 25C 82 91 dBc -55C to +125C 77 86 fIN= 30 MHz 86 fIN= 55 MHz 84 fIN= 70 MHz 25C 80 87 -55C to +125C 75 83 fIN= 100 MHz 84 fIN= 150 MHz 78 fIN= 225 MHz 74 Third-harmonic HD3 fIN= 10 MHz 25C 82 89 dBc -55C to +125C 77 88 fIN= 30 MHz 90 fIN= 55 MHz 79 fIN= 70 MHz 25C 80 85 -55C to +12

30、5C 75 82 fIN= 100 MHz 82 fIN= 150 MHz 80 fIN= 225 MHz 76 Worst-harmonic/spur (other than HD2 and HD3) fIN= 10 MHz 25C 88 dBc fIN= 70 MHz 25C 86 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLU

31、MBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/05613 REV A PAGE 7 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Test conditions unless otherwise specified Device type Limits Unit Min Typ Max ELECTRICAL CHARATERISTICS - Continued. 2/ Dynamic AC Characteristi

32、cs - Continued. Signal-to-noise + distortion SINAD fIN= 10 MHz 25C All 69 70 dBc -55C to +125C 66.5 70 fIN= 30 MHz 70 fIN= 55 MHz 69.5 fIN= 70 MHz 25C 68.5 69 -55C to +125C 65 69.5 fIN= 100 MHz 69 fIN= 150 MHz 69 fIN= 225 MHz 66.4 Total harmonic distortion THD fIN= 10 MHz 25C 80 85 dBc -55C to +125C

33、 76 83 fIN= 30 MHz 82 fIN= 55 MHz 77 fIN= 70 MHz 25C 77.5 81 -55C to +125C 74 79.5 fIN= 100 MHz 79 fIN= 150 MHz 75 fIN= 225 MHz 71.8 Effective number of bits ENOB fIN= 70 MHz 11.3 Bits Two-tone intermodulation distortion IMD f = 10.1 MHz, 15.1 MHz (-7 dBFS each tone) 85 dBc f = 30.1 MHz, 35.1 MHz (-

34、7 dBFS each tone) 85 f = 50.1 MHz, 55.1 MHz (-7 dBFS each tone) 88 Power Supply Total supply current ICCVIN= full-scale, fIN= 55 MHz AVDD= DRVDD= 3.3 V All 236 265 mA Analog supply current IAVDDVIN= full-scale, fIN= 55 MHz AVDD= DRVDD= 3.3 V 175 190 mA Output buffer supply current IDRVDDVIN= full-sc

35、ale, fIN= 55 MHz AVDD= DRVDD= 3.3 V 61 75 mA Power dissipation Analog only 578 627 mW Total power with 10 pF load on digital output to ground. 780 875 Standby power With clocks running 181 250 mW See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted with

36、out license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/05613 REV A PAGE 8 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Test conditions unless otherwise specified Device type Limits Unit Min Typ Max DIGITAL CHARAC

37、TERISTICS 2/ Digital Inputs High-level input voltage All 2.4 V Low-level input voltage 0.8 V High-level input current 10 A Low-level input current 10 A Input current for RESET -20 A Input capacitance 4 pF Digital Outputs 5/ Low-level output voltage fS= 125 MSPS, CLOAD= 10 pF 6/ All 0.3 V High-level

38、output voltage fS= 125 MSPS, CLOAD= 10 pF 6/ 3 V Output capacitance 3 pF TIMING CHARACTERISTICS 2/ Switching Specification Aperture delay tASee figure 4a. Input CLK falling edge to data sampling point. All 1 ns Aperture jitter (uncertainty) See figure 4a. Uncertainty in sampling instant. 300 fs Data

39、 setup time tSETUPSee figure 4a. Data valid to 50% of CLKOUT rising edge. 2 ns Data hold time tHOLDSee figure 4a. CLKOUT rising edge to data becoming invalid 1.7 ns Data latency tD(Pipe)See figure 4a. Input clock falling edge (on which sampling takes place) to input clock rising edge (on which the c

40、orresponding data is given out). 16.5 Clock cycles Propagation delay tPDISee figure 4a. Input clock rising edge to data valid. 7.5 ns Data rise time Data out 20% to 80%. 2.5 ns Data fall time Data out 20% to 80%. 2.5 ns Output enable (OE) to output stable delay 2 ms Serial Programming Interface Timi

41、ng Characteristics 7/ SCLK period tSCLKAll 50 ns SCLK duty cycle tWSCLK25% 50% 75% SEN to SCLK setup time tSLOADS8 ns SCLK to SEN hold time tSLOADH6 ns Data setup time tDS8 ns Data hold time tDH6 ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted w

42、ithout license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/05613 REV A PAGE 9 TABLE I. Electrical performance characteristics - Continued. 1/ 1/ Testing and other quality control techniques are used to the extent deemed necessary to assure prod

43、uct performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. 2/ Typical

44、(Typ), minimum (min), and maximum (max) values at room temperature is TA= 25C, full temperature range is TMIN= -55C to TMAX= +125C, sampling rate = 125 MSPS, 50% clock duty cycle, AVDD= DRVDD= 3.3 V, DLL On, -1 dBFS differential input, and 3-VPPdifferential clock, unless otherwise specified. 3/ 2 mA

45、 per input. 4/ See paragraph 1.4, Recommended operating conditions. 5/ For optimal performance, all digital output lines (D0: D13), including the output clock, should see a similar load. 6/ Equivalent capacitance to ground of (load + parasitics of transmission lines). 7/ Min, Typ, and Max values are

46、 characterized, but not production tested. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/05613 REV A PAGE 10 Case X D2/E2D1/E1D/Ee b1 161732334849640.08 MAA1SEAT

47、INGPLANE0.08SEEDETAIL AL1A2c0-7DETAIL AA3GAGEPLANETHERMAL PADSEE NOTE 4Dimensions Symbol Millimeters Inches Symbol Millimeters Inches Min Max Min Max Min Max Min Max A - 1.20 - 0.047 D/E 11.80 12.20 0.465 0.480 A1 0.95 1.05 0.037 0.041 D1/E1 9.80 10.20 0.386 0.402 A2 0.25 NOM 0.010 NOM D2/E2 7.50 TY

48、P 0.295 TYP A3 0.05 0.15 0.002 0.006 e 0.50 BSC 0.020 BSC b 0.17 0.27 0.007 0.011 L1 0.45 0.75 0.018 0.030 c 0.13 NOM 0.005 NOM NOTES: 1. All linear dimensions are in millimeters (inches). 2. This drawing is subject to change without notice. 3. Body dimensions do not include mold flash or protrusion. 4. This package is