DLA DSCC-DWG-V62 13618-2013 MICROCIRCUIT LINEAR DUAL PERIPHERAL NAND DRIVER MONOLITHIC SILICON.pdf

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1、 REVISIONS LTR DESCRIPTION DATE APPROVED Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 PMIC N/A PREPARED BY RICK OFFICER DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil/ Origi

2、nal date of drawing YY-MM-DD CHECKED BY RAJESH PITHADIA TITLE MICROCIRCUIT, LINEAR, DUAL PERIPHERAL NAND DRIVER, MONOLITHIC SILICON 13-11-07 APPROVED BY CHARLES F. SAFFLE SIZE A CODE IDENT. NO. 16236 DWG NO. V62/13618 REV PAGE 1 OF 13 AMSC N/A 5962-V067-13 Provided by IHSNot for ResaleNo reproductio

3、n or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13618 REV PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance dual peripheral NAND driver microcircuit, with an operating t

4、emperature range of -40C to +85C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/13618 - 01 X E Drawing Dev

5、ice type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 SN65472-EP Dual peripheral NAND driver 1.2.2 Case outline(s). The case outline(s) are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package sty

6、le X 8 MS-012-AA Plastic small outline 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladium Z Other Provided by IHSNot

7、for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13618 REV PAGE 3 1.3 Absolute maximum ratings. 1/ Supply voltage range (VCC) . 7 V maximum 2/ Input voltage (VIN) 5.5 V maximum Inter-emitter vo

8、ltage . 5.5 V maximum 3/ Off state output voltage (VOUT) 70 V Continuous collector or output current . 400 mA 4/ Peak collector or output current (tW10 ms, duty cycle 50%) 500 mA 4/ Absolute maximum junction temperature range (TJ) -40C to +150C Storage temperature range (TSTG) -65C to +150C 1.4 Reco

9、mmended operating conditions. 5/ Supply voltage (VCC) 4.75 V minimum 5 V nominal 5.25 V maximum High level input voltage (VIH) . 2 V minimum Low level input voltage (VIL) 0.8 V maximum Operating free-air temperature range (TA) . -40C to +85C Operating virtual junction temperature (TJ) -40C to +125C

10、1/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to

11、 absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ Unless otherwise specified, voltage values are with respect to the network GND. 3/ This is the voltage between two emitters, A and B. 4/ Both halves of these dual circuits may conduct rated current simultaneous

12、ly; however, power dissipation averaged over a short time interval must fall within the continuous dissipation rating. 5/ Use of this product beyond the manufacturers design rules or stated parameters is done at the users risk. The manufacturer and/or distributor maintain no responsibility or liabil

13、ity for product used beyond the stated limits. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13618 REV PAGE 4 1.5 Thermal characteristics. Thermal metric Symbol Case X Uni

14、t Thermal resistance, junction-to-ambient 6/ JA115.3 C/W Thermal resistance, junction-to-case (top) 7/ JC(TOP)59.7 C/W Thermal resistance, junction-to-board 8/ JB56.2 C/W Characterization parameter, junction-to-top 9/ JT13.5 C/W Characterization parameter, junction-to-board 10/ JB55.6 C/W _ 6/ The t

15、hermal resistance, junction-to-ambient under natural convection is obtained in a simulation on a JEDEC standard, High-K board, as specified in JESD51-7, in an environment described in JESD51-2a. 7/ The thermal resistance, junction-to-case (top) is obtained by simulating a cold plate test on the pack

16、age top. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. 8/ The thermal resistance, junction-to-board is obtained by simulating in an environment with a ring cold plate fixture to control the printed circuit board (PCB) temperature, as d

17、escribed in JESD51-8. 9/ Characterization parameter, junction-to-top (JT) estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining JA, using a procedure described in JESD51-2a (sections 6 and 7). 10/ Characterization parameter, junction-

18、to-board (JB) estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining JA, using a procedure described in JESD51-2a (sections 6 and 7). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA

19、 LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13618 REV PAGE 5 2. APPLICABLE DOCUMENTS AMERICAN NATIONAL STANDARDS INSTITUTE ANSI SEMI STANDARD G30-88 - Test Method for Junction-to-Case Thermal Resistance Measurements for Ceramic Packages (Applications for copies should b

20、e addressed to the American National Standards Institute, Semiconductor Equipment and Materials International, 1819 L Street, NW, 6 th floor, Washington, DC 20036 or online at http:/www.ansi.org) JEDEC Solid State Technology Association JESD 51-2a - Integrated Circuits Thermal Test Method Environmen

21、t Conditions Natural Convection (Still Air) JEDEC 51-7 - High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages JESD 51-8 - Integrated Circuits Thermal Test Method Environment Conditions Junction-to-Board JEDEC PUB 95 - Registered and Standard Outlines for Semiconductor Dev

22、ices (Applications for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or online at http:/www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 her

23、ein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and

24、recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outlin

25、e shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Truth table. The truth table shall be as shown in figure 3. 3.5.4 Logic diagram. The logic diagram shall be as shown in figure 4. 3.5.5 Timing waveforms and test circu

26、it. The timing waveforms and test circuits shall be as shown in figure 5. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13618 REV PAGE 6 TABLE I. Electrical performance ch

27、aracteristics. 1/ Test Symbol ConditionsTemperature, TA2/ Device type Limits Unit Min Max Input clamp voltage VIKVCC= 4.75 V, IIN= -12 mA -40C to +85C 01 -1.5 V +25C -1.2 typical High level output current IOHVCC= 4.75 V, VIH= 2 V, VOH= 70 V -40C to +85C 01 270 A Low level output voltage VOLVCC= 4.75

28、 V, VIL= 0.8 V, -40C to +85C 01 0.4 V IOL= 100 mA +25C 0.25 typical VCC= 4.75 V, VIL= 0.8 V, -40C to +85C 0.75 IOL= 300 mA +25C 0.5 typical Input current at maximum input voltage IINVCC= 5.25 V, VIN= 5.5 V -40C to +85C 01 1 mA High level input current IIHVCC= 5.25 V, VIN= 2.4 V -40C to +85C 01 44 A

29、Low level input current IILVCC= 5.2 5 V, VIN= 0.4 V -40C to +85C 01 -1.6 mA +25C -1 typical Supply current, outputs high ICCHVCC= 5.25 V, VIN= 5 V -40C to +85C 01 17 mA +25C 13 typical Supply current, outputs low ICCLVCC= 5.25 V, VIN= 0 V -40C to +85C 01 76 mA +25C 61 typical Switching characteristi

30、cs. VCC= 5 V, TA= +25C Propagation delay time, low to high level output tPLHIO= 200 mA, CL= 15 pF, +25C 01 65 ns RL= 50 , see figure 5 45 typical Propagation delay time, high to low level output tPHLIO= 200 mA, CL= 15 pF, +25C 01 50 ns RL= 50 , see figure 5 30 typical See footnotes at end of table.

31、Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13618 REV PAGE 7 TABLE I. Electrical performance characteristics Continued. 1/ Test Symbol ConditionsTemperature, TA2/ Device

32、 type Limits Unit Min Max Switching characteristics continued. VCC= 5 V, TA= +25C Transition time, low to high level output tTLHIO= 200 mA, CL= 15 pF, +25C 01 25 ns RL= 50 , see figure 5 13 typical Transition time, high to low level output tTHLIO= 200 mA, CL= 15 pF, +25C 01 20 ns RL= 50 , see figure

33、 5 10 typical High level output voltage after switching VOHVS= 55 V, IO= 300 mA, see figure 5 +25C 01 VS- 18 mV 1/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be t

34、ested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. 2/ All typical values are at VCC= 5 V and TA= +25C. Provided by IHSNot for ResaleNo reproduction

35、or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13618 REV PAGE 8 Case X FIGURE 1. Case outline. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME CO

36、LUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13618 REV PAGE 9 Case X continued. Symbol Dimensions Inches Millimeters Min Max Min Max A - 0.069 - 1.75 A1 0.004 0.010 0.10 0.25 b 0.012 0.020 0.31 0.51 c 0.005 0.010 0.13 0.25 D 0.189 0.197 4.80 5.00 E 0.150 0.157 3.80 4.00 E1 0.228 0.244 5.80 6

37、.20 e 0.050 BSC 1.27 BSC L 0.016 0.050 0.40 1.27 n 8 8 NOTES: 1. Controlling dimensions are inch, millimeter dimensions are given for reference only. 2. For dimension D, body length does not include mold flash, protrusion, or gate burrs. Mold flash, protrusion, or gate burrs shall not exceed 0.006 i

38、nch (0.15 mm) per end. 3. For dimension E, body width does not include interlead flash. Interlead flash shall not exceed 0.017 inch (0.43 mm) each side. 4. Falls with JEDEC MS-012-AA. FIGURE 1. Case outline - Continued. Provided by IHSNot for ResaleNo reproduction or networking permitted without lic

39、ense from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13618 REV PAGE 10 Device type 01 Case outline X Terminal number Terminal symbol 1 1A 2 1B 3 1Y 4 GND 5 2Y 6 2A 7 2B 8 VCCFIGURE 2. Terminal connections. Provided by IHSNot for ResaleNo reproduction or netw

40、orking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13618 REV PAGE 11 Inputs Output A B Y See note L L H (off state) L H H (off state) H L H (off state) H H L (on state) NOTE: Positive logic = Y = AB or A + B . FIGURE 3. Truth ta

41、ble. FIGURE 4. Logic diagram. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13618 REV PAGE 12 Switching times. NOTES: 1. The pulse generator has the following characterist

42、ics: PRR 1 MHz, ZO= 50 . 2. CLincludes probe and jig capacitance. Latch up test. NOTES: 1. The pulse generator has the following characteristics: PRR 1 MHz, ZO= 50 . 2. CLincludes probe and jig capacitance. FIGURE 5. Timing waveforms and test circuit. Provided by IHSNot for ResaleNo reproduction or

43、networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13618 REV PAGE 13 4. VERIFICATION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicated in the

44、ir internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPARATION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in ac

45、cordance with the manufacturers standard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient chara

46、cteristics of the device manufacturers data book. The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as

47、a guarantee of present or continued availability as a source of supply for the item. DLA Land and Maritime maintains an online database of all current sources of supply at http:/www.landandmaritime.dla.mil/Programs/Smcr/. Vendor item drawing administrative control number 1/ Device manufacturer CAGE code Transportation mode and quantity Top side marking Vendor part number V62/13618-01XE 01295 Tape of 75 65472 SN65472DEP 01295 Reel of 2500 65472 SN65472DREP 1/ The vendor item drawing establishes an administrative