ANSI STM5.5.1-2016 Electrostatic Discharge Sensitivity Testing C Transmission Line Pulse (TLP) C Device Level.pdf

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1、ANSI/ESD STM5.5.1-2016 Revision and Consolidation of ANSI/ESD STM5.5.1-2014 and ANSI/ESD SP5.5.2-2007 For Electrostatic Discharge Sensitivity Testing Transmission Line Pulse (TLP) Device Level EOS/ESD Association, Inc. 7900 Turin Road, Bldg. 3 Rome, NY 13440 An American National Standard Approved Ja

2、nuary 5, 2017ANSI/ESD STM5.5.1-2016 ESD Association Standard Test Method for Electrostatic Discharge Sensitivity Testing Transmission Line Pulse (TLP) Device Level EOS/ESD Association, Inc. Approved November 2, 2016 ANSI/ESD STM5.5.1-2016 Electrostatic Discharge Association (ESDA) standards and publ

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11、BLE FOR DAMAGES ARISING OUT OF, OR IN CONNECTION WITH, THE USE OR MISUSE OF ESDA STANDARDS OR PUBLICATIONS, EVEN IF ADVISED OF THE POSSIBILITY THEREOF. THIS IS A COMPREHENSIVE LIMITATION OF LIABILITY THAT APPLIES TO ALL DAMAGES OF ANY KIND, INCLUDING, WITHOUT LIMITATION, LOSS OF DATA, INCOME OR PROF

12、IT, LOSS OF OR DAMAGE TO PROPERTY, AND CLAIMS OF THIRD PARTIES. Published by: Electrostatic Discharge Association 7900 Turin Road, Bldg. 3 Rome, NY 13440 Copyright 2016 by EOS/ESD Association, Inc. All rights reserved No part of this publication may be reproduced in any form, in an electronic retrie

13、val system or otherwise, without the prior written permission of the publisher. Printed in the United States of America ISBN: 1-58537-290-0 CAUTION NOTICE DISCLAIMER OF WARRANTIES DISCLAIMER OF GUARANTY LIMITATION ON ESDAs LIABILITY ANSI/ESD STM5.5.1-2016 i (This foreword is not part of ESD Associat

14、ion Standard Test Method ANSI/ESD STM5.5.1-2016) FOREWORD This document defines a method for pulse testing to evaluate the voltage-current response of the component under test. This technique is known as “transmission line pulse” (TLP) testing. This document simultaneously describes the techniques t

15、raditionally known as TLP methods (pulse duration in the order of 100 ns), VF-TLP methods (pulse duration shorter than or equal to 10 ns), and long pulse TLP methods (pulse duration more than 200 ns). TLP testing techniques are being used for semiconductor process development, device and circuit des

16、ign and failure analysis. This technique or practice is being utilized on products in both wafer level and packaged environments. TLP testing is used as an ESD characterization tool to obtain voltage-current pulse characterization parameters, failure levels, and ESD metrics. The TLP technique is bei

17、ng used today as a standard measurement for ESD devices. The TLP system to the ESD engineer is a tool as critical as the “parameter analyzer” is to the semiconductor engineer. TLP systems are commercially available and can be made by engineers in a laboratory environment. With the usage of TLP data

18、for ESD characterization, technology benchmarking, and product quality evaluation, there is a need to have standard methodologies, failure criteria, and means of reporting to allow dialogue between semiconductor suppliers, vendors, and product customers. This document defines the standard test metho

19、d1 used today in the semiconductor industry for the TLP testing method and techniques in both industrial and academic institutions. It also covers the methods used to verify measurement accuracy and to perform system calibration. This document is intended to be used by electrical technicians, electr

20、ical engineers, semiconductor process and device engineers, ESD reliability and quality engineers, and circuit designers. The document is intended as a reference for the practices being used today. The context of this document is the application of TLP techniques for the electrical characterization

21、of semiconductor components. These semiconductor components can be single devices, a plurality of devices, integrated circuits, or semiconductor chips. This methodology is relevant to both active and passive elements. This test method is applicable to diodes, MOSFET devices, bipolar transistors, res

22、istors, capacitors, inductors, contacts, vias, wire interconnects and related components. This document covers transmission line based systems applying quasi-rectangular pulses with a wide range of pulse widths and rise times. All are referred to as TLP systems. Further sub-division is discussed in

23、the document. This document can also serve as a basis to describe variants of such systems, e.g. nonrectangular pulses or systems based on solid-state pulsers or source measurement units. This document was originally designated ANSI/ESD SP5.5.1-2004, and approved on February 22, 2004. ANSI/ESD STM5.

24、5.1-2008 was a revision and re-designation of ANSI/ESD SP5.5.1-2004 and was approved on February 24, 2008. ANSI/ESD STM5.5.1-2014 was a revision of ANSI/ESD STM5.5.1-2008 and was approved on August 26, 2014. The additional document being merged was designated ANSI/ESD SP5.5.2-2007 and was approved S

25、eptember 16, 2007. ANSI/ESD STM5.5.1-2016 is a revision, consolidation, and redesignation of ANSI/ESD STM5.5.1-2014 and ANSI/ESD SP5.5.2-2007; and was approved on November 2, 2016. 1 ESD Association Standard Test Method (STM): A definitive procedure for the identification, measurement and evaluation

26、 of one or more qualities, characteristics or properties of a material, product, system or process that yields a reproducible test result. ANSI/ESD STM5.5.1-2016 ii At the time ANSI/ESD STM5.5.1-2016 was prepared, the 5.5 (TLP) Device Testing Subcommittee had the following members: Theo Smedes, Chai

27、r NXP Semiconductors Robert Ashton ON Semiconductor Jon Barth Barth Electronics, Inc. Lorenzo Cerati STMicroelectronics Marcel Dekker MASER Engineering Farzan Farbiz Texas Instruments, Inc. Reinhold Gaertner Infineon Technologies AG Horst Gieser Fraunhofer EMFT Vaughn Gross Green Mountain ESD Labs,

28、Inc. Evan Grund Grund Technical Solutions, LLC Leo G. Henry ESDTLP Consultants Timothy Maloney Intel Corporation Thomas Meuse Thermo Fisher Scientific Paul Phillips Phasix ESD Bill Reynolds GLOBALFOUNDRIES Alan Righter Analog Devices Masanori Sawada HANWA Electronic Ind. Co., Ltd. Wolfgang Stadler,

29、TAS Rep Intel Deutschland GmbH Steven H. Voldman Steven H. Voldman LLC Scott Ward Texas Instruments, Inc. Terry Welsher Dangelmayer Associates Heinrich Wolf Fraunhofer EMFT ANSI/ESD STM5.5.1-2016 iii The following individuals contributed to the development of ANSI/ESD STM5.5.1-2014, ANSI/ESD STM5.5.

30、1-2008, ANSI/ESD SP5.5.2-2007, and/or ANSI/ESD SP5.5.1-2004. Robert Ashton ON Semiconductor Jon Barth Barth Electronics, Inc. Joseph Bernier Intersil Corporation David Bennett Thermo Electron Corporation Tilo Brodbeck Infineon Technologies Lorenzo Cerati STMicroelectronics Michael Chaine Micron Tech

31、nology, Inc. Marcel Dekker MASER Engineering Charvaka Duvvury Texas Instruments Marti Farris Intel Corporation Reinhold Gaertner Infineon Technologies AG Horst Gieser Fraunhofer EMFT Vaughn Gross Green Mountain ESD Labs, Inc. Hugh Hyatt Hyger Physics, Inc. Evan Grund Grund Technical Solutions, Inc.

32、Leo G. Henry ESDTLP Consultants Mike Hopkins Thermo Electron Corporation Mark Kelly Delphi Electronics the data collected in the average window will represent one I-V point on the DUT I-V curve. ANSI/ESD STM5.5.1-2016 16 8.5.8 Perform a post-stress evaluation measurement on the DUT. If the device fa

33、ils (see Annex B.1 and B.2 for guidelines), and if an automatic stop criterion is set, the test is complete. 8.5.9 If the device passes (see Annex B for guidelines) or there is not an automatic stop criterion, increase the pulse amplitude to the next desired level and repeat steps 8.5.6 to 8.5.8 unt

34、il the maximum desired pulse amplitude is reached. To minimize measurement error, it is necessary to set the desired step size to magnitudes consistent with the test structure response. NOTE: Depending on the DUT configuration and requirements, additional bias can be applied to the DUT terminals dur

35、ing application of the TLP pulse. External transients can lead to accidental triggering of the DUT when ground loops exist. Ground loops shall be avoided. ANSI/ESD STM5.5.1-2016 17 (This annex is not part of ESD Association Standard Test Method ANSI/ESD STM5.5.1-2016) Annex A (INFORMATIVE) TLP Desig

36、n Guidelines A.1 Transmission Line Cable-Based System A key distinction in transmission line pulse (TLP) test systems is the pulse source. The main components of a TLP system that utilizes a transmission line cable source include: a. Oscilloscope (see Section 5.1) b. Fixed Impedance Charged Transmis

37、sion Line (usually 50 ohms) c. High Voltage Switch d. High Voltage Power Supply e. Isolation of the power supply from the charging line f. Method to trigger the switch g. Attenuator for most TLP systems (see Section 5.7) h. Voltage and/or Current Probes (see Sections 5.2 and 5.3) i. Method of connec

38、ting a transmission line to the DUT j. Rise time filters (see Section 5.8) A.2 TLP Methods and System Classification Different design methodologies exist in TLP systems. For this section, the methods will be defined and the distinction between them highlighted. There are four fundamental TLP methodo

39、logies: current source, time domain reflection with overlapping incident and reflected pulse (TDR-O), time domain reflection with separated incident and reflected pulse (TDR-S), and time domain reflection and transmission (TDRT). These methods are compared in Table 7. The values are indicative only.

40、 Actual implementations may have different limitations. Table 7. TLP Methodologies and Parameters Typical Features Method of Transmission Line Pulsing (TLP) Current Source TDR-O TDR-S TDRT Impedance () Approximately 500 50 50 100 Maximum Current, short circuit* (A) 5 20 20 10 Pulse Width, FWHM 50 ns

41、 to 1 s, 100 ns typical greater than 10 ns, 100 ns typical shorter than 10 ns, 5 ns typical greater than 10 ns, 100 ns typical Rise Time, Tr greater than 3 ns, 10 ns typical greater than 100 ps, 10 ns typical 200 ps typical greater than 100 ps, 10 ns typical Reflections Slight Yes Yes Yes Voltage Re

42、flection Polarity Unipolar, never inverted Bipolar, first reflection inverted if DUT impedance 50 ohms Bipolar, first reflection inverted if DUT impedance 50 ohms Unipolar, never inverted ANSI/ESD STM5.5.1-2016 18 Typical Features Method of Transmission Line Pulsing (TLP) Current Source TDR-O TDR-S

43、TDRT Attenuation needed to reduce reflections No Yes (at least 6 dB) Yes Yes Two-channel Oscilloscope Yes Yes No (if current is calculated) Yes Reference Pulse Required No No (if both voltage and current are measured) Yes (incident pulse (=reference) is measured with the same scope channel) No *Base

44、d on a 1000 volts supply charging the transmission line. Use of attenuators in the DUT path requires higher voltages to obtain this current. Higher currents may be achieved with supplies that generate higher voltages. Additional attenuators may be needed at oscilloscope inputs. A.2.1 Current Source

45、TLP Method The Current Source TLP method is shown in Figure 7. In this method, there is a 500-ohm impedance in series with the DUT and a termination. A two-channel oscilloscope is used with a current probe (to measure current through the DUT) and voltage probe (in parallel with the DUT to measure DU

46、T voltage). Only minor reflections are observed and no reference pulse is required. Figure 7: Current Source TLP A.2.2 Time Domain Reflectometer TLP Method with overlapping pulses (TDR-O) The most commonly used 100 ns TLP configuration is TDR-O. In this TLP testing setup the current and/or voltage p

47、robes are placed relatively close to the DUT so that the electrical propagation time between the probes and the DUT are typically less than 15% of the pulse width. The oscilloscope receiving the probe signals will record a waveform that is first the incident pulse traveling toward the DUT and then t

48、he overlap of the incident with the reflected pulse coming back from the DUT (see Figure 4). While these two pulses are displaced in time from each other, DUT + _ H V I V 56 500 R LARGE R P V DUT = ( 50 + R P )/ 50 ) V I DUT = I (c orr ec t f or i nd uc t i v e p r ob e g ai n) S co p e (50 - o h m

49、inp u t s ) ANSI/ESD STM5.5.1-2016 19 they are both approximately constant during the TLP plateau period, and therefore their overlay can settle to a steady state of relatively constant voltages and currents. Waveforms are sampled during their constant or quasi-stable state overlapped period by averaging the waveforms during the measurement window. Since the waveforms are not time aligned due to the signal delay time between the measurement probes, the waveforms captured by the oscilloscope are only an approximation of the actual DUT voltage and current.