ISO IEC 10859-1997 Information technology - 8-bit backplane interface STEbus and mechanical core specifications for microcomputers《信息技术 8位底板接口 微处理器用的STEbus和机械心线.pdf

《ISO IEC 10859-1997 Information technology - 8-bit backplane interface STEbus and mechanical core specifications for microcomputers《信息技术 8位底板接口 微处理器用的STEbus和机械心线.pdf》由会员分享，可在线阅读，更多相关《ISO IEC 10859-1997 Information technology - 8-bit backplane interface STEbus and mechanical core specifications for microcomputers《信息技术 8位底板接口 微处理器用的STEbus和机械心线.pdf（98页珍藏版）》请在麦多课文档分享上搜索。

1、INTERNATIONAL STANDARD ISOIIEC 10859 Fi rst edition 1997-06 Information technology - 8-bit backplane interface: STEbus and mechanical core specifications for microcomputers Technologies de linformation - Interface de fond de panier 8 bits - Bus STE This material is reproduced from IS0 documents unde

2、r International Organization for Standardization (ISO) Copyright License number IHSIICC11996. Not for resale. No part of these IS0 documents may be reproduced in any form, electronic retrieval system or otherwise, except as allowed in the copyright law of the country of use, or with the prior writte

3、n consent of IS0 (Case postale 56,121 I Geneva 20, Switzerland, Fax +41 22 734 10 79), IHS or the IS0 Licensors members. Reference number ISOAEC 10859: 1997(E) STD-IS0 L0857-ENGL 3777 m 4853703 0723bLb U28 INTERNATIONAL STANDARD ISO/IEC 10859 First edition 1997-06 Information technology - 8-bit back

4、plane interface: STEbus and mechanical core specifications for microcomputers Technologies de linformation - hterface de fond de panier 8 bits - Bus STE O ISOAEC 1997 All rights reserved Unless otherwise specified, no part of this publication may be reproduced or utilized in any form or by any means

5、, electronic or mechanical, including photocopying and microfilm, without permission in writing from the publisher ISOAEC Copyright Office Case postale 56 CH-1211 Genve 20 Switzerland -2- CONTENTS 10859 O ISO/IEC:1997 FOREWORD . IEEE STANDARD FOR A 8-BIT BACKPLANE INTERFACE: STEBUS INTRODUCTION . Cl

6、ause 1 General 2 Functional description . 3 Signal lines . 4 Arbitration . 5 Data transfer protocol . 6 Inter-board signalling 7 Electrical specifications Appendices B A Applicable IEC specifications Recommended bus termination arrangement MECHANICAL CORE SPECIFICATIONS FOR MICROCOMPUTERS INTRODUCTI

7、ON . Clause 1 2 3 4 5 6 7 8 9 10 11 12 Scope . Object References . General arrangement Euroboard matrix Euroboard sizes Position of plug-in unit mounted connectors (Board types and box type) Plug-in unit description . Plug-in unit dimensions . Backplane design and mounting positions . Su bracks Envi

8、ronmental specifications . Page 3 4 5 9 10 16 18 32 36 42 43 Page 45 46 46 46 47 49 50 55 58 58 59 83 93 10859 O ISO/IEC:1997 -3- Information technology - 8-bit backplane interface: STEbus and mechanical core specifications for microprocessors FOREWORD IS0 (the International Organization for Standar

9、dization) and IEC (the International Electrotechnical Commission) form the specialized system for worldwide standardization. National bodies that are members of IS0 or IEC participate in the development of International Standards through technical committee established by the respective organization

10、 to deal with particular fields of technical activity. IS0 and IEC technical committees collaborate in fields of mutual interest. Other international organizations, governmental and non-governmental, in liaison with IS0 and IEC, also take part in the work. In the field of information technology, IS0

11、 and IEC have established a joint technical committee, ISO/IEC JTC1. Draft International Standards adopted by the joint technical committee are circulated to national bodies for voting. Publication as an International Standard requires approval by at least 75 % of the national bodies casting a vote.

12、 International Standard ISO/IEC 10859 was prepared by joint technical committee ISO/IEC JTC1, Information technology, SC 26: Microprocessor system. This standard is a merging of IEEE Std 1000-1987 and IEEE 1101-1987. It has been submitted to the National Committees for vote under the Fast Track Proc

13、edure. The numbering of the original clauses remains unchanged. STD - IS0 10857-ENGL 1797 W 4853703 0723b19 837 9 -4- 1 0859 O ISOA EC: 1 997 INTRODUCTION TO IEEE STANDARD FOR AN 8-BIT BACKPLANE INTERFACE: STEBUS The initial concept for STEbus was to produce a European version of the STDBus using th

14、e Eurocard form factor with the DIN41612 connector. From that concept STE became known as STD- European. When IEEE formed Working Group P1000 the brief specified a Standard 8-Bit Backplane Interface. At the inaugural meeting of Working Group P1000 it quickly became apparent that the opportunity was

15、there to create a completely new, modern, high-performance 8-Bit bus, and all ideas of merely repinning the old STDbus were rapidly forgotten. At the initial meeting of P1000 it was decided that the bus should be a part of the same family as VMEbus and Futurebus and as such should be an asynchronous

16、 bus with multimaster capability. Today it is often referred to as the baby brother of VMEbus. Unlike VMEbus though it was to be processor and manufacturer independent. This has proven to be an excellent decision as today there are many varied types of processor available on STEbus, from microcontro

17、llers such as 8031, through Intels 8085, 8088, and 80188; National Semiconductors 32008 and 32016; Motorolas 6809, 68000, and 68008; Zilogs 280 and 2280; Hitachis 64180, and the Inmos Transputer with the promise of more to come. A presentation was made to a packed audience at the IEE in London, Engl

18、and in early 1983. It met with critical acclaim. The first article about STEbus was also published about this time in an international magazine (EDN May 26, 1983). Work continued internationally and in late 1984 Draft D3.1 was produced. This draft eradicated the daisy-chain bus request mechanism of

19、D2.0 in favour of a simple solution that allowed position independence of cards in the rack. This was the first firm specification and encouraged more manufacturers to look at the bus seriously. Among them were BICC-Vero, a major manufacturer of Eurocard enclosures and backplanes, and British Teleco

20、m, the UKs Telephone Utility. Market ground zero was early 1985 and since this time the number of manufacturers has continued to grow from 18 companies in Spring 1986 to more than 30 in mid-1987, with over 700 products available. Much credit and praise is due Tim Elsmore who first conceived the idea

21、 for STEbus during his employment with GMT Electronic Systems Ltd. Paul Borrill was instrumental in negotiating with IEEE the formation of Working Group P1000 and Bill Shields was appointed Chairman. This standard was prepared by Working Group P1 O00 of the Microprocessor Standards Committee. - - ST

22、D-IS0 L0857-ENGL 1997 4851903 0723b20 559 D 10859 O ISO/IEC:1997 -5- Information technology - 2) specify those device-independent electrical, mechanical, and functional interface parameters that must be met so as to effect unambiguous communication between system elements and to effect physical comp

23、atibility; 3) specify the terminology and definitions related to the specification; 4) enable the interconnection of a wide variety of independently manufactured boards within a single functional system; 5) define a standard that places the minimum number of restrictions on the performance character

24、istics of boards within a conforming system; 6) allow microcomputer system users of relatively modest experience to assemble modularly expandable computer systems with a high probability of success. 1.4 Definitions The following general definitions apply throughout this standard. Additional detailed

25、 definitions are given where appropriate. 1.4.1 General system terms compatibility: The degree to which boards may be interconnected and used without modification when designed according to the specifications contained within this standard. interface: A shared boundary between two or more systems, o

26、r between two or more elements within a system, through which information is conveyed. interface system: The device-independent electrical, mechanical, and functional interface elements required for unambiguous communication between two or more devices. Typical elements include: 10859 O ISOAEC: 1997

27、 -7- - driver and receiver circuitry; - signal line descriptions; - timing and control conventions; - communication protocols; - functional logic circuits. system: A set of interconnected boards that achieve a specified objective by the performance of designated functions. 1.4.2 Signals and paths ad

28、dress: The reference to a unit of data or the value represented by the address lines while ADRSTB“ is active. addressed board: A board that recognizes its address while ADRSTB* is active. arbitration: The means whereby masters compete for control of the bus and the process by which a master is grant

29、ed control of the bus. backplane: A printed circuit board (pcb) on which connectors are mounted, into which boards or plug-in units are inserted. block transfer: A sequence of data transfers, in the same direction, that occur during a single bus transaction. board: A printed circuit board (pcb) that

30、 complies with this standard. bus: A signal line or set of lines used by an interface system to connect a number of devices, and over which information is conveyed. byte: A set of eight signals, individually referred to as bits, which are operated on as a unit. handshake: An interlocked sequence of

31、signals between interconnected boards in which each board waits for an acknowledgement of its previous signal before proceeding. high state: The more positive voltage level used to represent one of two logical binary states. low state: The more negative voltage level used to represent one of two log

32、ical binary states. module: A plug-in unit consisting of one or more boards that contains at least one bus interface conforming to this standard, which plugs into the backplane. protocol: The signalling rules used to convey information or commands between boards connected to the bus. release: The ac

33、tion of a transmitter in ceasing to hold a signal line in the asserted state. sequence: An indivisible bus transaction comprising one or more transfers. settling time: The time taken for a signal line to settle unambiguously to a logical state when making a transition from one state to another. sign

34、al: The physical representation of data. -8- 10859 O ISO/IEC:1997 Function Electrical Logical CM High 1 True Low O False High Z - signal level: The relative magnitude of a signal when considered in relation to an arbitrary reference. The unit of representation used within this standard is the volt.

35、State Active, asserted Active, released Inactive signal line: One of a set of signal conductors in an interface system used to transfer data among interconnected boards. signal parameter: That element of an electrical quantity whose values or sequence of values convey information. tenure: The time d

36、uring which a master has control of the bus. transaction: The combination of data transfer sequences controlled by a master during a single bus tenure. transfer: The movement of a single byte of data from the current master to the addressed slave(s) or from the addressed slave to the master. 1.4.3 G

37、eneric signai names Throughout this standard bus request and acknowledge signals and attention request signals are sometimes referred to as BUSRQn, BUSAKn*, and ATNRQn* respectively. Such general references are equivalent to specific references RUSRQO* or BUSRQ1 etc. 1.4.4 Notation for bus signais T

38、hroughout this standard signals on a particular bus are referred to collectively using the form A. This notation should be taken as an abbreviation of all of the address bus signals from AI9 through to AO inclusive. In addition to the address bus signals, the notation is also used for the data lines

39、 (for example, Dc70), the common lines (for example, CM), the attention request lines (for example, ATNRQ*), the bus request lines (for example, BUSRQ*) and the bus acknowledge lines (for example, BUSAK*). 1.5 Logical and electrical state relationships Throughout this standard the term asserted is u

40、sed to indicate the logical true state of the particular signal referenced. The corresponding term negated, however, is not used because it comprises a potentially ambiguous representation when describing signals, which may be low or high true. ADRSTB Low High Hiah Z 1 True 1 False - Active, asserted Active, released Inactive