JEDEC JESD75-4-2004 Ball Grid Array Pinout for 1- 2- and 3-Bit Logic Functions《1 2和3位逻辑功能的球状网络阵列插脚引线》.pdf

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1、JEDEC SOLID STATE TECHNOLOGY ASSOCIATIONJESD75-4MARCH 2004JEDECSTANDARDBall Grid Array Pinout for 1-, 2-, and 3-Bit Logic FunctionsNOTICEJEDEC standards and publications contain material that has been prepared, reviewed, and approvedthrough the JEDEC Council level and subsequently reviewed and appro

2、ved by the EIA General Counsel.JEDEC standards and publications are designed to serve the public interest through eliminatingmisunderstandings between manufacturers and purchasers, facilitating interchangeability andimprovement of products, and assisting the purchaser in selecting and obtaining with

3、 minimum delay theproper product for use by those other than JEDEC members, whether the standard is to be used eitherdomestically or internationally.JEDEC standards and publications are adopted without regard to whether or not their adoption mayinvolve patents or articles, materials, or processes. B

4、y such action JEDEC does not assume any liability toany patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC standards orpublications.The information included in JEDEC standards and publications represents a sound approach to productspecification and application, pr

5、incipally from the solid state device manufacturer viewpoint. Within theJEDEC organization there are procedures whereby a JEDEC standard or publication may be furtherprocessed and ultimately become an EIA standard.No claims to be in conformance with this standard may be made unless all requirements

6、stated in thestandard are met.Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication shouldbe addressed to JEDEC Solid State Technology Association, 2500 Wilson Boulevard, Arlington, VA22201-3834, (703)907-7559 or www.jedec.org.Published byJEDEC Solid Stat

7、e Technology Association 20042500 Wilson BoulevardArlington, VA 22201-3834This documentmay be downloaded free of charge, however JEDEC retains the copyright on this material. By downloading this file the individual agrees not to charge for or resell the resulting material.Price: Please refer to the

8、current Catalog of JEDEC Engineering Standards and Publications or call Global EngineeringDocuments, USA and Canada (1-800-854-7179), International (303-397-7956)Printed in the U.S.A.All rights reservedPLEASE! DONT VIOLATE THE LAW! This document is copyrighted by the Electronic Industries Alliance a

9、nd may not be reproduced without permission. Organizations may obtain permission to reproduce a limited number of copies through entering into a license agreement. For information, contact: JEDEC Solid State Technology Association 2500 Wilson Boulevard Arlington, Virginia 22201-3834 or call (703) 90

10、7-7559 JEDEC Standard No. 75-4Page 1BALL GRID ARRAY PINOUTS STANDARDIZED FOR 1-, 2-, AND 3-BIT LOGIC FUNCTIONS(Formerly JEDEC Board B allot JCB-03-65, formulated under the cognizance of the JC-40 Committee on Digital Logic.)1 ScopeThis standard defines device pinout for 1-, 2- and 3-bit wide logic f

11、unctions. This pinout specifically applies to the conversion of Dual-Inline-Packaged (DIP) 1-, 2- and 3-bit logic devices to DSBGA-packaged 1-, 2- and 3-bit logic devices. The purpose of this document is to provide a pinout standard for 1-, 2- and 3-bit logic devices offered in 5-, 6- or 8-ball Die-

12、Sized Ball Grid Array (DSBGA) packages for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use.2 Terms and definitions (for the purpose of this document)DIP: Dual In-line Pin Package (gull-wing)SSOP: Shrink Small-Outline Package; 0.65-mm lead

13、pitch; 5.3-mm wide body (MO-150)TSSOP: Thin Shrink Small-Outline Package; 0.65-mm lead pitch; 4.4-mm wide body (MO-153)TVSOP: Thin Very Small-Outline Package; 0.4-mm lead pitch; 4.4-mm wide body (MO-194)DSBGA:Die-Sized Ball Grid Array; 0.5-mm ball pitch (MO-211)3 Pinout standard3.1 DescriptionThe fo

14、llowing criteria shall be used to convert existing 1-, 2- and 3-bit logic device functions offered in 5-, 6- and 8-pin DIP packages (e.g. SSOP, TSSOP, TVSOP) to 1-, 2- and 3-bit logic device functions offered in the 5-, 6- and 8-ball DSBGA packages:A. Attributes for the DSBGA package area as indicat

15、ed below:5-Ball, 0.50-mm ball pitch with 0.90-mm 1.40-mm body size and 3-row 2-column ball matrix, depopulated from 6-ball, MO-211, Variation EA.6-Ball, 0.50-mm ball pitch with 0.90-mm 1.40-mm body size and 3-row 2-column ball matrix, MO-211, Variation EA.8-Ball, 0.50-mm ball pitch with 0.90-mm 1.90

16、-mm body size and 4-row 2-column ball matrix, MO-211, Variation EA.B. The pinout conversions shall be in accordance with the diagrams shown in sections 3.2, 3.4 and 3.6. Each deviceshall be pinned out based on its present package/pinout and the pinout tables in sections 3.3, 3.5, and 3.7.3.2 5-ball

17、DSBGA (MO-211)Figure 1 Pinout configuration123BOTTOM VIEW54JEDEC Standard No. 75-4Page 23 Pinout standard (contd)3.3 Pin conversion from 5-pin DIP to 5-ball DSBGAThe pinout adopts the naming convention of logic devices in 5-pin DIP packages. The signal nomenclature used in this table is intended to

18、define the functionality of each pin and not require that a specific naming convention be followed. Each product vendor is free to name the pin according to their own conventions, provided that the functionality of the device is not altered from what is specified here. NOTE 1The function designation

19、 refers to the part designation of a series of commercial logic parts common in the industry. This number is normally preceded by a series of manufacturer-specific characters to make up a complete part designation.NOTE 2DNU means Do Not Use. This designation requires that the printed circuit landing

20、-pad for this device terminal remain unconnected to any signal or supply potential. It must remain an open circuit. This device terminal might be connected to active or inactive circuitry within the device.NOTE3.4 6-ball DSBGA (MO-211)Figure 2 Pinout configurationTable 1 5-pin pinout tableFunction(S

21、ee Note) Description Pin Numbers1 2 3 4 51G00 Single 2-input NAND gate A B GND Y VDD1G02 Single 2-input NOR gate A B GND Y VDD1G04 Single inverter DNU A GND Y VDD1GU04 Single unbuffered inverter DNU A GND Y VDD1G05 Inverter with open-drain output DNU A GND Y VDD1G06 Inverter with open-drain output D

22、NU A GND Y VDD1G07 Single buffer/driver with open-drain output DNU A GND Y VDD1G08 Single 2-input AND gate A B GND Y VDD1G14 Single inverter with Schmitt-trigger input DNU A GND Y VDD1G17 Single buffer/driver with Schmitt-trigger input DNU A GND Y VDD1G32 Single 2-input OR gate A B GND Y VDD1G34 Sin

23、gle buffer DNU A GND Y VDD1G38 Single 2-input NAND gate with open-drain output A B GND Y VDD1G66 Single analog switch I/O I/O GND OE VDD1G79 D-type flip-flop with Q output D CK GND Q VDD1G80 D-type flip-flop with Q output D CK GND Q VDD1G86 Single 2-input XOR gate A B GND Y VDD1G125 Single buffer/dr

24、iver with 3-state outputs OE A GND Y VDD1G125 Single bus switch OE A GND B VDD1G126 Single buffer/driver with 3-state outputs OE A GND Y VDD1G240 Single inverter with 3-state outputs OE A GND Y VDD1G384 Single bus switch A B GND OE VDD123BOTTOM VIEW645JEDEC Standard No. 75-4Page 33 Pinout standard (

25、contd)3.5 Pin conversion from 6-pin DIP to 6-ball DSBGAThe pinout adopts the naming convention of logic devices in 6-pin DIP packages. The signal nomenclature used in this table is intended to define the functionality of each pin and not require that a specific naming convention be followed. Each pr

26、oduct vendor is free to name the pin according to their own conventions, provided that the functionality of the device is not altered from what is specified here.NOTE 1 The function designation refers to the part designation of a series of commercial logic parts common in the industry. This number i

27、s normally preceded by a series of manufacturer-specific characters to make up a complete part designation.NOTE 2 DNU means Do Not Use. This designation requires that the printed circuit landing-pad for this device terminal remain unconnected to any signal or supply potential. It must remain an open

28、 circuit. This device terminal might be connected to active or inactive circuitry within the device.Table 2 6-pin pinout tableFunction DescriptionPin Numbers1 2 3 4 5 62G04 Dual inverter 1A GND 2A 2Y VDD 1Y2GU04 Dual unbuffered inverter 1A GND 2A 2Y VDD 1Y2G06 Dual inverter with open-drain outputs 1

29、A GND 2A 2Y VDD 1Y2G07 Dual buffer/driver with open-drain outputs 1A GND 2A 2Y VDD 1Y1G10 Single 3-input NAND gate A GND B Y VDD C1G11 Single 3-input AND gate A GND B Y VDD C2G14 Dual inverter with Schmitt-trigger inputs 1A GND 2A 2Y VDD 1Y2G16 Dual buffer 1A GND 2A 2Y VDD 1Y2G17 Dual buffer/driver

30、with Schmitt-trigger inputs 1A GND 2A 2Y VDD 1Y1G18 1-of-2 non-inverting demux with 3-state output S GND A 1Y VDD 0Y1G19 1-of-2 decoder/multiplexer A GND OE 1Y VDD 0Y1G27 Single 3-input NOR A GND B Y VDD C2G34 Dual buffer/driver 1A GND 2A 2Y VDD 1Y1G57 Universal configurable 2-input gate In1 GND In0

31、 Y VDD In21G58 Universal configurable 2-input gate In1 GND In0 Y VDD In21G97 Universal configurable 2-input gate In1 GND In0 Y VDD In21G98 Universal configurable 2-input gate In1 GND In0 Y VDD In21G157 Single 2-input non-inverting multiplexer In1 GND In0 Y VDD S1G158 Single 2-input inverting multipl

32、exer In1 GND In0 Y VDD S1G175 Single D-type flip-flop CK GND D Q VDD CLR1G332 Single 3-input OR A GND B Y VDD C1G386 Single 3-input XOR A GND B Y VDD C1G373 Single D-type latch LE GND D Q VDD OE1G374 Single D-type flip-flop CK GND D Q VDD OE1G3157 SPDT analog switch I/O2 GND I/O1 COM VDD S1G3257 2-t

33、o-1 bus-switch multiplexer B2 GND B1 A VDD SJEDEC Standard No. 75-4Page 43 Pinout standard (contd)3.6 8-ball DSBGA (MO-211)Figure 3 Pinout configuration3.7 Pin conversion from 8-pin DIP to 8-ball DSBGAThe pinout adopts the naming convention of logic devices in 8-pin DIP packages. The signal nomencla

34、ture used in this table is intended to define the functionality of each pin and not require that a specific naming convention be followed. Each product vendor is free to name the pin according to their own conventions, provided that the functionality of the device is not altered from what is specifi

35、ed here.Table 3 8-pin pinout tableFunc-tion DescriptionPin Numbers1 2 3 4 5 6 7 82G00 Dual 2-input NAND gate 1A 1B 2Y GND 2A 2B 1Y VDD2G02 Dual 2-input NOR gate 1A 1B 2Y GND 2A 2B 1Y VDD2G08 Dual 2-input AND gate 1A 1B 2Y GND 2A 2B 1Y VDD2G32 Dual 2-input OR gate 1A 1B 2Y GND 2A 2B 1Y VDD2G38 Dual 2

36、-input NAND gate with open-drain output1A 1B 2Y GND 2A 2B 1Y VDD2G53 Dual analog MUX/DEMUX COM INH GND GND S I/O2 I/O1 VDD2G66 Dual analog switch 1I/O 1I/O 2OE GND 2I/O 2I/O 1OE VDD2G74 Single D-type flip-flop CK D Q GND Q CLR PRE VDD2G79 Dual D-type flip-flop 1CK 1D 2Q GND 2CK 2D 1Q VDD2G80 Dual D-

37、type flip-flop with inverting Q outputs1CK 1D 2Q GND 2CK 2D 1Q VDD2G86 Dual 2-input XOR gate 1A 1B 2Y GND 2A 2B 1Y VDD2G125 Dual buffer/driver with 3-state outputs1OE 1A 2Y GND 2A 1Y 2OE VDD2G126 Dual buffer/driver with 3-state outputs1OE 1A 2Y GND 2A 1Y 2OE VDD2G132 Dual 2-input NAND gate with schm

38、itt-trigger inputs1A 1B 2Y GND 2A 2B 1Y VDD2G139 Single 2-to-4 decoder A B Y4 GND Y3 Y2 Y1 VDD2G157 Single MUX/DEMUX A B Y GND Y S G VDD2G240 Dual inverting buffer with 3-state outputs1OE 1A 2Y GND 2A 1Y 2OE VDD2G241 Dual buffer/driver with 3-state outputs1OE 1A 2Y GND 2A 1Y 2OE VDD1234BOTTOM VIEW87

39、65JEDEC Standard No. 75-4Page 5NOTE 1 The function designation refers to the part designation of a series of commercial logic parts common in the industry. This number is normally preceded by a series of manufacturer-specific characters to make up a complete part designation.NOTE 2 DNU means Do Not

40、Use. This designation requires that the printed circuit landing-pad for this device terminal remain unconnected to any signal or supply potential. It must remain an open circuit. This device terminal might be connected to active or inactive circuitry within the device.2G244 Dual buffer/driver with 3

41、-state outputs1OE 1A 2Y GND 2A 1Y 2OE VDD3G04 Triple inverter 1A 3Y 2A GND 2Y 3A 1Y VDD3GU04 Triple unbuffered inverter 1A 3Y 2A GND 2Y 3A 1Y VDD3G05 Triple inverter with open-drain outputs1A 3Y 2A GND 2Y 3A 1Y VDD3G06 Triple inverter with open-drain outputs1A 3Y 2A GND 2Y 3A 1Y VDD3G07 Triple buffe

42、r/driver with open-drain outputs1A 3Y 2A GND 2Y 3A 1Y VDD3G14 Triple inverter with Schmitt-trigger inputs1A 3Y 2A GND 2Y 3A 1Y VDD3G17 Triple buffer/driver with Schmitt-trigger inputs1A 3Y 2A GND 2Y 3A 1Y VDD3G34 Triple buffer/driver 1A 3Y 2A GND 2Y 3A 1Y VDDTable 3 8-pin pinout tableFunc-tion DescriptionPin Numbers1 2 3 4 5 6 7 8JEDEC Standard No. 75-4Page 64 Reference to other applicable JEDEC standards and publicationsJEP95, JEDEC Registered and Standard Outlines for Solid State and Related Product