JEDEC JESD659C-2017 Failure-Mechanism-Driven Reliability Monitoring.pdf
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1、JEDEC STANDARD Failure-Mechanism-Driven Reliability Monitoring JESD659C (Revision of JESD659B, February 2007, Reaffirmed June 2011) JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board
2、 of Directors level and subsequently reviewed and approved by the JEDEC legal counsel. JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, a
3、nd assisting the purchaser in selecting and obtaining with minimum delay the proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally. JEDEC standards and publications are adopted without regard to whether or not their adopti
4、on may involve patents or articles, materials, or processes. By such action JEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC standards or publications. The information included in JEDEC standards and publications repres
5、ents a sound approach to product specification and application, principally from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard or publication may be further processed and ultimately become an ANSI standard. No claims to be
6、in conformance with this standard may be made unless all requirements stated in the standard are met. Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication should be addressed to JEDEC at the address below, or refer to www.jedec.org under Standards and Do
7、cuments for alternative contact information. Published by JEDEC Solid State Technology Association 2017 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 This document may be downloaded free of charge; however JEDEC retains the copyright on this material. By downloading this file the i
8、ndividual agrees not to charge for or resell the resulting material. PRICE: Contact JEDEC Printed in the U.S.A. All rights reserved PLEASE! DONT VIOLATE THE LAW! This document is copyrighted by JEDEC and may not be reproduced without permission. For information, contact: JEDEC Solid State Technology
9、 Association 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 or refer to www.jedec.org under Standards-Documents/Copyright Information. -ii- JEDEC Standard No. 659C -i- FAILURE-MECHANISM-DRIVEN RELIABILITY MONITORING CONTENTS Page Introduction ii 1 Scope 1 2 Terms and definitions 1 3
10、 Process controls 3 4 Identifying failure mechanisms 3 5 When to establish a monitor 4 6 What a monitor includes 4 7 Control action system 5 8 Monitor optimization 6 Annex A (informative) Differences between JESD659C and JESD659B 7 -ii- FAILURE-MECHANISM-DRIVEN RELIABILITY MONITORING Introduction Th
11、is standard presents a methodology for monitoring component and subassembly reliability. It can be of use to suppliers and users interested in known reliability as an attribute of the component through the production life. Under this standard, the suite of metrics is tailored to monitor the failure
12、mechanisms which limit the reliability. This is distinguished from a stress-driven monitor approach in which a fixed suite of acceptance stresses or other testing are prescribed and applied without customization according the failure mechanisms for the component or subassembly. JEDEC Standard No. 65
13、9C Page 1 FAILURE-MECHANISM-DRIVEN RELIABILITY MONITORING (From JEDEC Board ballot JCB-07-19, formulated under the cognizance of JC-14.3 Committee on Silicon Devices Reliability Qualification and Monitoring.) 1 Scope This standard describes essential requirements for a reliability monitor for compon
14、ents and subassemblies based on the measurement of failure mechanisms which limit reliability. It applies through the post-qualification production period. Both intrinsic (wearout and systematic) and extrinsic (defect-based) sources of failure are addressed. 2 Terms and definitions For the purposes
15、of this standard, the following definitions apply. Definitions marked by a asterisk (*) are taken from JESD557, Statistical Process Control Systems. They are replicated here for completeness. characteristic*: A distinguishing feature of a process or its output on which variables or attributes data c
16、an be collected. common cause*: A source of natural variation that affects all the individual values of the process output being studied. In control chart analysis it appears as part of the random process variation. control limits*: The maximum allowable variation of a process characteristic due to
17、common causes alone. Variation beyond a control limit may be evidence that special causes affecting the process. Control limits are calculated from process data and are usually represented as a line (or lines) on a control chart. They are not to be confused with engineering specification limits. cri
18、tical failure mechanism: In semiconductor devices, any potential physical failure mechanism that exhibits one or more of the following: intermittency (e.g., bond lifts), increasing failure rate (e.g., electromigration), and inconsistent or unpredictable failure kinetics (e.g., stress-induced metal v
19、oiding) extrinsic failure mechanism: (1) A failure mechanism caused by an error occurring during the design, layout, fabrication, or assembly process or by a defect in the fabrication or assembly materials. (2) A failure mechanism that is directly attributable to a defect created during manufacturin
20、g. failure: (1) The loss of the ability of a component to meet the electrical or physical performance specifications that (by design or testing) it was intended to meet. (2) A component that has failed. failure mechanism from fabrication processes: A physical failure mechanism in which all products
21、with the same wafer fabrication process, design rules, and processing line are treated as a homogeneous population for the purpose of statistical reliability monitoring independent of package technology, material, construction, and type. JEDEC Standard No. 659C Page 2 2 Terms and definitions (contd)
22、 failure mechanism from assembly: A physical failure mechanism in which all products with the same assembly technology, including assembly material, assembly construction, and package type and built on the same assembly line are treated as a homogeneous population for the purpose of statistical reli
23、ability monitoring independent of the fabrication process and line. intrinsic failure mechanism: (1) A failure mechanism caused by a natural deterioration in the materials or the manner in which the materials are combined during fabrication or assembly processes that are within specification limits.
24、 (2) A failure mechanism attributable to natural deterioration of materials processed per specification. node*: A definable point in the process at which form, fit, or function of the product or service is altered. nonconformity*: A specific occurrence of a condition that does not conform to specifi
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