JEDEC JESD64-A-2000 Standard for Description of 2 5 V CMOS Logic Devices with 3 6 V CMOS Tolerant Inputs and Outputs《具有3 6V CMOS容忍输入输出的2 5V CMOS逻辑设备的描述规范》.pdf

《JEDEC JESD64-A-2000 Standard for Description of 2 5 V CMOS Logic Devices with 3 6 V CMOS Tolerant Inputs and Outputs《具有3 6V CMOS容忍输入输出的2 5V CMOS逻辑设备的描述规范》.pdf》由会员分享，可在线阅读，更多相关《JEDEC JESD64-A-2000 Standard for Description of 2 5 V CMOS Logic Devices with 3 6 V CMOS Tolerant Inputs and Outputs《具有3 6V CMOS容忍输入输出的2 5V CMOS逻辑设备的描述规范》.pdf（11页珍藏版）》请在麦多课文档分享上搜索。

1、JEDECSTANDARDStandard for Description of 2.5 VCMOS Logic Devices with 3.6 VCMOS Tolerant Inputs and OutputsJESD64-A(Revision of JESD64)OCTOBER 2000JEDEC SOLID STATE TECHNOLOGY ASSOCIATIONNOTICEJEDEC standards and publications contain material that has been prepared, reviewed, andapproved through the

2、 JEDEC Board of Directors level and subsequently reviewed and approvedby the EIA General Counsel.JEDEC standards and publications are designed to serve the public interest through eliminatingmisunderstandings between manufacturers and purchasers, facilitating interchangeability andimprovement of pro

3、ducts, and assisting the purchaser in selecting and obtaining with minimumdelay the proper product for use by those other than JEDEC members, whether the standard is tobe used either domestically or internationally.JEDEC standards and publications are adopted without regard to whether or not their a

4、doptionmay involve patents or articles, materials, or processes. By such action JEDEC does not assumeany liability to any patent owner, nor does it assume any obligation whatever to parties adoptingthe JEDEC standards or publications.The information included in JEDEC standards and publications repre

5、sents a sound approach toproduct specification and application, principally from the solid state device manufacturerviewpoint. Within the JEDEC organization there are procedures whereby an JEDEC standard orpublication may be further processed and ultimately become an ANSI/EIA standard.No claims to b

6、e in conformance with this standard may be made unless all requirements stated inthe standard are met.Inquiries, comments, and suggestions relative to the content of this JEDEC standard orpublication should be addressed to JEDEC Solid State Technology Association, 2500 WilsonBoulevard, Arlington, VA

7、 22201-3834, (703)907-7560/7559 or www.jedec.orgPublished byJEDEC Solid State Technology Association 20002500 Wilson BoulevardArlington, VA 22201-3834This document may be downloaded free of charge, however EIA retains thecopyright on this material. By downloading this file the individual agrees not

8、tocharge for or resell the resulting material.PRICE: Please refer to the currentCatalog of JEDEC Engineering Standards and Publications or call Global EngineeringDocuments, USA and Canada (1-800-854-7179), International (303-397-7956)Printed in the U.S.A.All rights reservedPLEASE!DONT VIOLATETHELAW!

9、This document is copyrighted by the Electronic Industries Alliance and may not bereproduced without permission.Organizations may obtain permission to reproduce a limited number of copiesthrough entering into a license agreement. For information, contact:JEDEC Solid State Technology Association2500 W

10、ilson BoulevardArlington, Virginia 22201-3834or call (703) 907-7559JEDEC Standard No. 64-APage 1STANDARD FOR DESCRIPTION OF 2.5 V CMOS LOGIC DEVICESWITH 3.6 V CMOS TOLERANT INPUTS AND OUTPUTS(From JEDEC Board Ballot JCB-00-21, formulated under the cognizance of JC-40 Committeeon Digital Logic.)1 Int

11、erface standard1.1 PurposeThe purpose is to provide a standard for 2.5 V nominal supply voltage logic devices foruniformity, multiplicity of sources, elimination of confusion, ease of device specification, andease of use. This specification provides for compatibility between devices operating betwee

12、neither the Standard Range of 1.8 V to 2.7 V or the optional Extended Range of 1.65 V to 2.7 Vsupply voltages, as well as over-voltage tolerance with devices operating at 3.6 V.1.2 ScopeThis standard defines dc interface parameters and test loading for digital devices based on 2.5 V(nominal) power s

13、upply levels.2 Definitions2.1 PrefixesPrefixes “54” or “74” immediately preceding family name indicate the operating temperaturerange. For example, 54XXX refers to the Military (MIL) version of devices which are specifiedover the temperature range of 55 C to 125 C. 74XXX refers to the Commercial (CO

14、ML)version of devices which are specified over 40 C to 85 C.JEDEC Standard No. 64-APage 23 Standard specifications3.1 Absolute maximum continuous ratings (Notes 1,2)Supply Voltage VDD 0.5 V to 3.6 VDC Input Voltage VIN . -0.5 V to 4.1 VDC Output Voltage Vout. . -0.5 V to 4.1 VStorage Temperature ran

15、ge . . -65 C to 150 CNOTES1 Absolute maximum continuous ratings are those values beyond which damage to thedevice may occur. Exposure to these conditions or conditions beyond those indicated mayadversely affect device reliability. Functional operation under these conditions is not implied.2 Under tr

16、ansient conditions these ratings may be exceeded as defined elsewhere in thisspecification.3.2 Recommended operating conditionsStandard Range Extended Range(1)Symbol ParameterMin Max Min MaxUnitVDDSupply Voltage 1.8 2.7 1.65 2.7 VVINVoltage Applied to input pins -0.3 3.6 -0.3 3.6 Voutputs enabled 0

17、VDD0VDDVVOUTVoltage applied tooutput or I/O pins.outputs high-Z 0 3.6 0 3.6 V74 Series -40 85 -40 85 CTAOperating free-airtemperature54 Series -55 125 -55 125 Ct/v Input transition rise or fall rate(2)010010ns/VNOTES1 Compatibility with the Extended Range specification is optional.2 As measured betw

18、een 0.7 V and 1.7 V.JEDEC Standard No. 64-APage 33 Standard specifications (contd)3.3 DC specificationsStandard Range Extended Range(1)Symbol Parameter ConditionMin Max Min MaxUnitVDD 2.3V 0.7 VDD0.7 VDDVIHHigh-level input voltageVDD 2.3V 1.7 1.7VVDD 2.3V 0.2 VDD0.2 VDDVILLow-level input voltageVDD

19、2.3V0.7 0.7VVDD= MIN IOH=-100 uA VDD-0.2 VDD-0.2VDD= 2.3 V IOH=-1 mA 2.0 2.0 VVOHHigh-level input voltageVDD=2.3 V IOH=-8 mA 1.8 1.8VDD= MIN IOL= 100 uA 0.2 0.2VDD= 2.3 V IOL= 1 mA 0.4 0.4 VVOLLow-level output voltageVDD=2.3 V IOL= 8 mA 0.6 0.6Input leakage current VDD = MINVI =3.6 V or GND10 10 AOf

20、f-state leakagecurrent(2)VDD = MINVO =3.6 V or GND100 100 AIDDStatic Supply Current VDD = MAXVI =VDDor GNDIO=0 (Outputs open)20 20 ANOTES1 Compatibility with the Extended Range specification is optional.2 For I/O pins, IOZincludes the input leakage.JEDEC Standard No. 64-APage 44 Test circuit and swi

21、tching waveformsTest circuit component values:CL= 30 pF or equivalent (includes jig and probe capacitance)RL= R1= 500 RT= ZOUTof pulse generator (typically 50 )VIN= 0 to VDD.tr= tf= 2.0 ns (10% to 90%) unless otherwise specified.Parameter Tested Switch PositiontPLHOpentPHLOpentPZHGNDtPZL2x VDDtPHZGN

22、DtPLZ2x VDDFigure 1 Test circuitJEDEC Standard No. 64-APage 54 Test Circuit and switching waveforms (contd)NOTE The outputs are measured one at a time, with one transition per measurementFigure 2 Switching waveformsJEDEC Standard No. 64-APage 65 Reference to other applicable JEDEC standards and publicationsJEDEC Standard No. 8-5, 2.5 V 0.2 V (Normal Range), and 1.8 V to 2.7 V (Wide Range)Power Supply Voltage and Interface Standard for Nonterminated Digital Integrated Circuit(EIA/JESD8-5).