JEDEC JEP121A-2006 Requirements for Microelectronic Screening and Test Optimization《微电子闪变和测试优化要求》.pdf
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1、JEDEC STANDARD Requirements for Microelectronic Screening and Test Optimization JEP121A (Revision of JEP121, April 1995, Reaffirmed September 20003) OCTOBER 2006 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and ap
2、proved through the JEDEC Board of Directors level and subsequently reviewed and approved by the JEDEC legal counsel. JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability
3、and improvement of products, and assisting the purchaser in selecting and obtaining with minimum delay the proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally. JEDEC standards and publications are adopted without regard
4、to whether or not their adoption may involve patents or articles, materials, or processes. By such action JEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC standards or publications. The information included in JEDEC sta
5、ndards and publications represents a sound approach to product specification and application, principally from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard or publication may be further processed and ultimately become an A
6、NSI standard. No claims to be in conformance with this standard may be made unless all requirements stated in the standard are met. Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication should be addressed to JEDEC at the address below, or call (703) 907-
7、7559 or www.jedec.org Published by JEDEC Solid State Technology Association 2006 2500 Wilson Boulevard Arlington, VA 22201-3834 This document may be downloaded free of charge; however JEDEC retains the copyright on this material. By downloading this file the individual agrees not to charge for or re
8、sell the resulting material. PRICE: Please refer to the current Catalog of JEDEC Engineering Standards and Publications online at http:/www.jedec.org/Catalog/catalog.cfm Printed in the U.S.A. All rights reserved PLEASE! DONT VIOLATE THE LAW! This document is copyrighted by JEDEC and may not be repro
9、duced without permission. Organizations may obtain permission to reproduce a limited number of copies through entering into a license agreement. For information, contact: JEDEC Solid State Technology Association 2500 Wilson Boulevard Arlington, Virginia 22201-3834 or call (703) 907-7559 JEDEC Public
10、ation No. 121A Page 1 REQUIREMENTS FOR MICROELECTRONIC SCREENING AND TEST OPTIMIZATION (From JEDEC Board Ballot, JCB-06-60, formulated under the cognizance of the JC-13.2 Subcommittee on Mircoelectronic Devices.) 1 Scope This document defines the methodology for the optimization (elimination, reduct
11、ion, or alternative approach) of the MIL-PRF-38535 screening and testing requirements for MIL-PRF-38535, Classes Q and V, Microcircuits. Inherent in this methodology is the application of “In-line Process Controls“ and “SPC“ techniques to the applicable manufacturing processes. This document include
12、s the process for initial approval and subsequent maintenance of the testing and screening optimizations. The purpose of this document provides the basis for the optimization of 100% screening/stress operations and sample inspection test activities. This document is designed to assist the manufactur
13、er in optimizing the test flow while maintaining and/or improving assurance of providing high quality and reliable product in an efficient manner. This will allow for optimization of testing that is not adding value, hence, reducing cycle time and costs. 2 Referenced documents 2.1 Military specifica
14、tions MIL-PRF-38535, Integrated Circuits (Microcircuits) Manufacturing, General Specification For 2.2 Military Standards MIL-STD-883 (Test Method Standard Microcircuits) 2.3 EIA Documents/publications ANSI/EIA Standard No. 557, Statistical Process Control Systems EIA-625 Requirements for Handling El
15、ectrostatic- Discharge-Sensitive (ESDS) Devices JEDEC publication No. 132, Process Characterization Guideline JEDEC Publication No. 121A Page 2 3 General Requirements 3.1 Test Optimization Foundation The manufacturer has to establish the foundation for “Test Optimization“ before implementing these o
16、ptimizations into the manufacturing and/or test flow. The manufacturing flow shall have an SPC system in place and an underlying philosophy that assures continuous improvement. Each critical operation relative to optimization of test shall have controls sufficient to ensure product meets the Technol
17、ogy Conformance Inspection (TCI) requirements of MIL-PRF-38535. The applicable Level I, II, and III quality characteristics controls defined herein shall be in place for the test to be eliminated. A facility granted approval for optimization of tests shall pursue efforts toward continuous improvemen
18、t. This assumes changes to the approved system and associated critical operations will occur. As changes to Level I, II and III quality characteristics control system are implemented, the manufacturer shall assure that sufficient evaluations have been performed to prevent the generation of defects t
19、hat would result in degradation in product performance at a test that has been optimized. The manufacturers control system shall be sensitive to detrimental trends or shifts in the process that may appear in the product. Changes in the Level I, II and III quality characteristics control system shall
20、 be communicated to the qualifying activity in accordance with the specified change notification requirements. This publication primarily focuses on the required controls to eliminate screens and/or tests. The manufacturer may use other “test optimization” approaches to detect potential quality and
21、reliability issues, such as; modify manufacturing flow to minimize handling and reduce risk of potential product damage, use in-process controls or tests for earlier detection, develop alternative sampling plans, or develop alternative test techniques to effectively identify and/or screen defective
22、product. These alternative approaches should consider the Level I, II, and III quality characteristics described herein, and understand the potential causes and detection of process quality or reliability defects as applicable in establishing the alternative test plans. 3.2 Statistical Process Contr
23、ol (SPC) System An SPC system must be fully implemented before test optimization is initiated. A comprehensive SPC system must first be developed in accordance with EIA Standard 557. JEDEC Publication 132 can be used as a guideline to assist the manufacturer in characterizing processes. 3.3 Quality
24、characteristics Once the SPC system is fully implemented, the manufacturer can start the optimization of screens and or tests. The first step in this process is the identification of the primary quality characteristics that are to be controlled. The “Quality Characteristics“ are those measurable pro
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