DLA SMD-5962-95713 REV B-2007 MICROCIRCUIT DIGITAL RADIATION HARDENED CMOS PROGRAMMABLE INTERVAL TIMER MONOLITHIC SILICON《抗辐射数字的互补金属氧化物半导体可编程计时器硅单片电路线型微电路》.pdf

《DLA SMD-5962-95713 REV B-2007 MICROCIRCUIT DIGITAL RADIATION HARDENED CMOS PROGRAMMABLE INTERVAL TIMER MONOLITHIC SILICON《抗辐射数字的互补金属氧化物半导体可编程计时器硅单片电路线型微电路》.pdf》由会员分享，可在线阅读，更多相关《DLA SMD-5962-95713 REV B-2007 MICROCIRCUIT DIGITAL RADIATION HARDENED CMOS PROGRAMMABLE INTERVAL TIMER MONOLITHIC SILICON《抗辐射数字的互补金属氧化物半导体可编程计时器硅单片电路线型微电路》.pdf（17页珍藏版）》请在麦多课文档分享上搜索。

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Changes in accordance with NOR 5962-R127-98. 98-07-08 Monica L. Poelking B Update boilerplate to current MIL-PRF-38535 requirements and to include radiation hardness assurance requirements. - LTG 07-04-17 Thomas M. Hess REV SHET REV B B SHET 15 1

2、6 REV STATUS REV B B B B B B B B B B B B B B OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Thomas M. Hess DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY Thomas M. Hess COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE

3、BY ALL DEPARTMENTS APPROVED BY Monica L. Poelking AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 96-01-16 MICROCIRCUIT, DIGITAL, RADIATION HARDENED CMOS PROGRAMMABLE INTERVAL TIMER, MONOLITHIC SILICON AMSC N/A REVISION LEVEL B SIZE A CAGE CODE 67268 5962-95713 SHEET 1 OF 16 DSCC FOR

4、M 2233 APR 97 5962-E339-07 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-95713 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. Thi

5、s drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radi

6、ation Hardness Assurance (RHA) levels is reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 R 95713 01 V X C Federal stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2)Device class designatorCase outline (see 1.2.4) Lead finish (see 1.2.5) / (see

7、1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the ap

8、propriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 82C54RH Radiation hardened CMOS programmable interval timer 1.2.3 Device class designator. The device cla

9、ss designator is a single letter identifying the product assurance level as follows: Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certi

10、fication and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style J GDIP1-T24 or CDIP2-T24 24 Dual-in-line X CDFP4-F24 24 Ceramic flat pack 1.2.5 Lead finish. The lead

11、 finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-95713 DEFENSE SUPPLY CENTER COLUMBUS COLUMB

12、US, OHIO 43218-3990 REVISION LEVEL B SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 1/ Supply voltage (VDD) +7.0 V dc Input or output voltage range . VSS-0.3 V dc to VDD+0.3 V dc Storage temperature range (TSTG) -65C to +150C Junction temperature (TJ). +175C Thermal resistance, junction

13、-to-case (JC) Case J +6C/W Case X +4C/W Thermal resistance, junction-to-ambient (JA) Case J +40C/W Case X +60C/W Maximum package power dissipation at TA= +125C (PD) 2/ Case J +1.25 W Case X +0.83 W Maximum lead temperature (soldering, 10 seconds) +300C 1.4 Recommended operating conditions. Operating

14、 supply voltage range (VDD) 4.5 V dc to +5.5 V dc Operating temperature range (TA) -55C to +125C Input low voltage range (VIL) 0 V dc to +0.8 V dc Input high voltage range (VIH). VDD-1.5 V dc to VDD1.5 Radiation features. Maximum total dose available (Dose rate = 50 300 rads(Si)/sec) . 100K Rads(Si)

15、 Transient upset 108Rads(Si)/sec 3/ Single event upset (SEU). 22 MeV/(mg/cm2) 3/ Single event latchup (SEL). 60 MeV/(mg/cm2) 3/ 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the ext

16、ent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Metho

17、d Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/assist.daps.d

18、la.mil/quicksearch/ or http:/assist.daps.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) _ 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degr

19、ade performance and affect reliability. 2/ If device power exceeds package dissipation capability, provide heat sinking or derate linearly (the derating is based on JA) at a rate of 25.0 mW/C for case J and 16.7 mW/C for case X. 3/ Limits are guaranteed by design or process, but not production teste

20、d unless specified by the customer through the purchase order or contract. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-95713 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET

21、 4 DSCC FORM 2234 APR 97 2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. AMERICAN SOCIETY FOR TESTING AND MATERIALS (ASTM

22、) ASTM F1192 - Standard Guide for the Measurement of Single Event Phenomena (SEP) Induced by Heavy Ion Irradiation of semiconductor Devices. (Copies of these documents are available online at http:/www.astm.org or from ASTM International, 100 Barr Harbor Drive, P.O. Box C700, West Conshohocken, PA 1

23、9428-2959). 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3.

24、 REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit,

25、or function as described herein. The individual item requirements for device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions s

26、hall be as specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.4 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on f

27、igure 1. 3.2.3 Block diagram. The block diagram shall be as specified on figure 2. 3.2.4 Timing waveforms and test circuit. The timing waveforms and test circuit shall be as specified on figure 3. 3.2.5 Radiation exposure circuit. The radiation exposure circuit shall be as specified on figure 4. 3.3

28、 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table IA and shall apply over the full ambient operating temperature range. 3.4 Electri

29、cal test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical tests for each subgroup are defined in table IA. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For p

30、ackages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordanc

31、e with MIL-PRF-38535. Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-95713 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 4321

32、8-3990 REVISION LEVEL B SHEET 5 DSCC FORM 2234 APR 97 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. The compliance mark for device class M shall be a “C“ as required in MIL-PRF-38535, appendix A. 3.6 Certi

33、ficate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of compliance shall be required from a manufacturer in ord

34、er to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturers product meets, for device classes Q and V, the requirements of

35、MIL-PRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with eac

36、h lot of microcircuits delivered to this drawing. 3.8 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product (see 6.2 herein) involving devices acquired to this drawing is required for any change that affects this drawing. 3.9 Verification and rev

37、iew for device class M. For device class M, DSCC, DSCCs agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 3.10 Microcircuit group assign

38、ment for device class M. Device class M devices covered by this drawing shall be in microcircuit group number 105 (see MIL-PRF-38535, appendix A). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-95713 DEFENSE

39、 SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 6 DSCC FORM 2234 APR 97 TABLE IA. Electrical performance characteristics. Test Symbol Conditions 1/ -55C TA +125C unless otherwise specified Group A subgroups Device type Limits Unit Min MaxTTL output current, high IOH1VDD= 4.5

40、 V, VO= 3.0 V VIN= 0 V or 4.5 V 1, 2, 3 All -2.5 mA CMOS output current, high IOH2VDD= 4.5 V, VO= 4.1 V VIN= 0 V or 4.5 V 1, 2, 3 All -100 A Output current, low IOLVDD= 4.5 V, VO= 0.4 V VIN= 0 V or 4.5 V 1, 2, 3 All 2.5 mA Input leakage current, high IIH-1.0 1.0 Input leakage current, low IILVDD= 5.

41、5 V, VIN= 0 V or 5.5 V Pins: 9, 11, 14-16, 18-23 1, 2, 3 All -1.0 1.0 A Output leakage current, high IOZH-10 10 Output leakage current, low IOZLVDD= 5.25 V, VIN= 0 V or 5.5 V Pins: 1-8 1, 2, 3 All -10 10 A Standby power supply current IDDSBVDD= 5.5 V, VIN= GND or VDDIO= 0 mA, Counters programmed 1,

42、2, 3 All 20.0 A Operating power supply current IDDOPVDD= 5.5 V, VIN= GND or VDDIO= 0 mA CLK0 = CLK1 = CLK2 = 5 MHz 1, 2, 3 All 12.0 mA Input capacitance CINSee 4.4.1c VDD= open, f = 1 MHz Measurement referenced to GND 4 All 15 pF Output capacitance COUTSee 4.4.1c VDD= open, f = 1 MHz Measurement ref

43、erenced to GND 4 All 15 pF I/O capacitance CI/OSee 4.4.1c VDD= open, f = 1 MHz Measurement referenced to GND 4 All 20 pF Functional tests See 4.4.1b VDD= 4.5 V and 5.5 V VIN= GND or VDD, f = 1 MHz 7, 8 All Noise immunity functional tests See 4.4.1b VDD= 5.5 V VIN= GND or VDD 1.5 V and VDD= 4.5 V VIN

44、= 0.8 V or VDD7, 8 All Address stable before RD tAVRL9, 10, 11 All 75 ns CS stable before RD tSLRL9, 10, 11 All 0 ns Address hold time after RD tRHAX9, 10, 11 All 0 ns RD pulse width tRLRH9, 10, 11 All 240 ns Data delay from RD tRLDV9, 10, 11 All 200 ns Command recovery time tRHRLVDD= 4.5 V and 5.5

45、V 9, 10, 11 All 320 ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-95713 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 7 DSCC FORM 2234 APR

46、 97 TABLE IA. Electrical performance characteristics Continued. Test Symbol Conditions 1/ -55C TA +125C unless otherwise specified Group A subgroups Device type Limits Unit Min MaxWRITE CYCLE Address stable before WR tAVWL9, 10, 11 All 0 ns CS stable before WR tSLWL9, 10, 11 All 0 ns Address hold ti

47、me after WR tWHAX9, 10, 11 All 0 ns WR pulse width tWLWH9, 10, 11 All 240 ns Data setup time before WR tDVWH9, 10, 11 All 225 ns Data hold time after WR tWHDX9, 10, 11 All 35 ns Command recovery time tWHWLVDD= 4.5 V and 5.5 V 9, 10, 11 All 320 ns CLOCK AND GATE Clock period tCLCL9, 10, 11 All 200 ns

48、 High pulse width tCHCL9, 10, 11 All 100 ns Low pulse width tCLCH9, 10, 11 All 100 ns Gate width high tGHGL9, 10, 11 All 80 ns Gate width low tGLGH9, 10, 11 All 80 ns Gate setup time to CLK tGVCH9, 10, 11 All 80 ns Gate hold time after CLK tCHGX9, 10, 11 All 80 ns Output delay from CLK tCLOV9, 10, 11 All 240 ns Output delay from gate tGLOV9, 10, 11 All 200 ns Data delay from address read tAVAV9, 10, 11 All 275 ns Output delay from WR high tWHOVVDD= 4.5 V and 5.5 V 9, 10, 11 All 260 ns TIMING REQUIREMENTS RD to data float 2/ tRHDZVDD= 4.5 V and 5.