DLA SMD-5962-94533-1994 MICROCIRCUIT DIGITAL CMOS 32-BIT MICROPROCESSOR MONOLITHIC SILICON《硅单片 32位微处理器 氧化物半导体数字微型电路》.pdf

《DLA SMD-5962-94533-1994 MICROCIRCUIT DIGITAL CMOS 32-BIT MICROPROCESSOR MONOLITHIC SILICON《硅单片 32位微处理器 氧化物半导体数字微型电路》.pdf》由会员分享，可在线阅读，更多相关《DLA SMD-5962-94533-1994 MICROCIRCUIT DIGITAL CMOS 32-BIT MICROPROCESSOR MONOLITHIC SILICON《硅单片 32位微处理器 氧化物半导体数字微型电路》.pdf（20页珍藏版）》请在麦多课文档分享上搜索。

1、I SMD-5962-94533 999999b 00b2134 i182 DEFENCE EXETKNICS SUPPLY CENTER mrlm, mo 45444 MICROCIRCUIT, DIGITAL, CMOS, 32-BIT MICROPROCESSOR, MONOLITHIC SILICON SIZE CAGE CODE 59 62-94533 B 67268 SHEET 1 OF 19 5962-E305-94 Provided by IHSNot for ResaleNo reproduction or networking permitted without licen

2、se from IHS-,-,-5qb2-94533 779999b 0062335 019 1.1 m. This drawing forms a part of a one part - one part nunber docunentation system (see 6.6 herein). Two product assurance classes consisting of military high reliability (device classes P and M) and space application (device class V), and a choice o

3、f case outlines and lead finishes are available and are reflected in the Part or Identifying Nunber (PIN). 1.2.1 of MIL-STD-883, tlProvisions for the use of MIL-STD-883 in conjunction with conpliant non-JAN devicest1. available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in

4、the PIN. Device class M microcircuits represent non-JAN class B microcircuits in accordance with When 1.2 u. lhe PIN shall be as shown in the following exemple: 94533 Federal RHA Itii Devi ce Device Case Lead 11 stock class designator type ci ass out 1 ine finish designator (see 1.2.1) (see 1.2.2) d

5、es i gnator (see 1.2.4) (see 1.2.5) / (see 1.2.3) / Drawing nurber L 1.2.1 RHA designator. Device class M RHA marked devices shall meet the MIL-1-38535 appendix A specified RHA leveis and shall be marked with the appropriate RHA designator. MIL-1-36535 specified RHA Levels and shall be marked with t

6、he appropriate RHA designator. non-RHA device. Device classes P and V RHA marked devices shall meet the A dash (-) indicates a 1.2.2 Device tmecsl. The device typeCs) shall identify the circuit function as follows: Devi ce tm Generic nunber Circuit function STANDARDIZED MILITARY DRAWING DEFENSE ELEC

7、TRONICS SUPPLY CENTER DAYTON, OHIO 45444 o1 02 SIZE 5962-94533 A SIO ON SHEEF 2 80386SX-16 80386SX-20 32-Bit Microprocessor 32-Bit Microprocessor 1.2.3 Device class designator. The device class designator shall be a single letter identifying the product assurance level as follows: I Device class Dev

8、ice reauirements docunentation I M Vendor self-certification to the requirements for non-JAN class 8 microcircuits in accordance with 1.2.1 of MIL-STD-883 Q or V Certification and qual if i cati on to UIL- I-38535 1.2.4 Case wtline(s1. The case outline(s) shall be as designated in MIL-STD-1835 and a

9、s follows: Outline letter Descriptive designator Terminals Packarie style Pin Grid Array X CMGAS-P88 a8 I 1.2.5 Lead finish. The lead finish shail be as specified in MIL-STD-883 (see 3.1 herein) for class M or MIL-1-38535 for classes P and V. Finish letter llxll shall not be marked on the microcircu

10、it or its packaging. The llXtl Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-5962-94533 W 9999996 0062336 T55 I STANDARD1 ZED SIZE MILITARY DRAWING A DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 ms1ONLEvEL 1.3 Absolute maxim ratings. 1/

11、 Storage Tenperature Range . -65C to +150“C Supply Voltage with respect to Grwnd . -0.W dc to 6.5 V dc Voltage on Any Pin with respect to Grd . -0.5V dc to Vcc + 0.5 V dc Maxim Power Dissipation . 1.6U Lead Ternperatwe (soldering 10 seconds) Thermal Resistance, Junction-to-case (OJC): Junction tenpe

12、rature (TJ) . +150“C 300C Case Y See MIL-STO-1835 1.4 Recamiended owratins conditions. Case Operating Temperature Range -5SC to +125“C Supply Voltage, Vcc Frequency of operation: 4.75 V dc to 5.25 V dc Device O1 16 HHz Device 02 20 MHz 1.5 Diaital logic testing for device classes and V. Fault covera

13、ge measurement of manufacturing logic tests (MIL-STO-883, test method 5012) 98.5 percent 2. APPLICABLE DOCUMENTS 2.1 Govermnt specification. standards, bulletin, and handbook. Unless otherwise specified, the following specification, standards, bulletin, and handbook of the issue Listed in that issue

14、 of the Department of Defense Index of Specifications and Standards specified in the solicitation, form a part of this drawing to the extent specified herein. 5962-94533 SHEET 3 SPECIFICATION MI LI TARY MIL-1-38535 - Integrated Circuits, Manufacturing, General Specification for. STANDARDS MILITARY M

15、IL-STD-883 - Test Methods and Procedures for Microelectronics. MIL-STD-973 - Configuration Management. MIL-STO-1835 - Microcircuit Case Outlines. BULLET IN MILITARY MIL-BUL-103 - List of Standardized Military Drawings (SMDs). HANDBOOK MI LI TARY MIL-HDBK-780 - Standardized Military Drawings. (Copies

16、 of the specification, standards, killetin, and handbook required by manufacturers in connection with specific acquisition functions should be obtained from the contracting activity or as directed by the contracting activity.) In the event of a conflict between the text of this drauing and the refer

17、ences cited herein, the text of this drawing shall take precedence. 2.2 Order of precedence. DESC FQRM 193A JTJL 91 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-5962-94533 H 9999996 0062337 993 H I STANDARD1 ZED SIZE MILITARY DRAWING A DEFENSE

18、 ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 ms1ONLEvEL I 3. REQUIREMENTS 3.1 lhe individual item requirements for device class M shall be in accordance uith 1.2.1 of MIL-STD-883, “Provisions for the use of MIL-STO-883 in conjunction with compliant non-JAN devices“ and as specified herein. device m

19、anufacturers Quality Management (QM) plan, and as specified herein. specified in MIL-STO-883 (see 3.1 herein) for device class M and MIL-1-38535 for device classes Q and V and herein. The case outline(s) shall be in accordance with 1.2.4 herein. Item requirements. The individual item requirements fo

20、r device classes Q and V shall be in accordance uith MIL-1-38535, the 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as 3.2.1 Case outIine(s1. 3.2.2 Terminal connections. 3.2.3 Functional block diaaram(s1. 3.2.4 Radiation exliosure circu

21、it. 3.3 lhe terminal connections shall be as specified on figure 1. The fwctional block diagram(s) shall be as specified on figure 2. lhe radiation exposure circuit shall be as specified when available. Electrical wrformance characteristics and postirradiation parameter limits. Unless atherwise spec

22、ified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full case operating tenperature range. lhe electrice1 tests for each subgrolp are defined in table 1. accordance with MIL-STD-883 (see 3.1 herein). MIL-B

23、UL-103. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table 11. Marking for device class M shall be in 3.5 Marking. lhe part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked as listed in

24、Marking for device classes Q and V shall be in accordance with MIL-1-38535. 3.5.1 Certification/cmliance mark. The compliance mark for device class M shall be a Wo as required in MIL-STO-883 (see 3.1 herein). in MIL-1-38535. The certification mark for device classes 9 and V shall be a “QMLto or W as

25、 required 3.6 Certificate of cwliance. For device class M, a certificate of conpliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-BUL-103 (see 6.7.2 herein). classes Q and V, a certificate of conpliance shall be required from a QML-38535 listed

26、 manufacturer in order to supply to the requirements of this drauing (see 6.7.1 herein). The certificate of cmpliance submitted to DESC-EC prior to listing as an approved source of supply for this drawing shall affirm that the manufacturers product meets, for device class M, the requirements of MIL-

27、STD-883 (see 3.1 herein), or for device classes 9 and V, the requirements of MIL-1-38535 and the requirements herein. 3.1 herein) or for device classes and V in MIL-1-38535 shall be provided with each lot of microcircuits delivered to this drawing. (see 6.2 herein) involving devices acquired to this

28、 drawing is required for any change as defined in MIL-STD-973. For device 3.7 Certificate of conformance. A certificate of conformance as required for device class M in MIL-STD-883 (see 3.8 Notification of change for device class M. For device class M, notification to DESC-EC of change of product 3.

29、9 Verification and revieu for device class M. For device class M, DESC, DESCs agent, and the acquiring activity Offshore docunentation retain the option to review the manufacturers facility and applicable required docunentation. shall be made available onshore at the option of the reviewer. microcir

30、cuit group rider 105 (see MIL-1-38535, appendix A). 3.10 Microcircuit group assigrment for device class W. Device class M devices covered by this drawing shall be in 4. QUALITY ASSURANCE PROVISIONS 4.1 Sawlins and inspection. For device class M, sampling and inspection procedures shall be in accorda

31、nce with MIL-STD-883 (see 3.1 herein). uith MIL-1-38535 and the device manufacturers QM plan. For device classes Q and V, sampling and inspection procedures shall be in accordance 5962-94533 SHEET 4 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-Tes

32、t Input low voltage Input high voltage CLKZ input Low voltage CLKZ input high voltage Output low voltage 1 A23-A1 , D15-DO Output low voltage BHE, BLE, ADS, HLDA, U/R, D/C, WIO, LOCK Output high voltage A23-A1, D15-DO Output high voltage A23-A1, D15-DO Output high voltage BHE, BLE, U/R, D/C, M/IO, L

33、OCK, ADS, HLDA Output high voltage BHE, BLEI W/R, D/C, M/iO, LOCK, ADS, HLDA Input leakage current BUSY, AND ERROR) (all pins except PEREP, Input leakage current I/ PEREP Input leakage current 9,10,11 t 28 I t26 I Reset hold time PEREP, ERROR, BUSY o/ B/ hold time t30 9,10,11 o1 02 STANDARD1 ZED MIL

34、ITARY DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 I o: 9,10,11 SIZE 5962-94533 A REVISIONLEVEL SHEEr 8 1 :; 9,10,11 1 :; 9,10,11 I t29 I PEREQ, ERROR, BUSY g/ B/ setup time I 9,10,11 I O1 02 Limits Unit ;I Ins ng pins are active low: 2J Tested initially and at process and design cha

35、nges. in table I. 3/ PEREQ input has an internal pull-down resistor. 9 BUSY# and ERROR# inputs each have an internai pull-up resistor. z/ I max measurement at uorst case load, frequency, Vcc end temperature. - 6/ doat condition occurs when maximm output current becomes less than IL0 in magnitude, fl

36、oat timings are NOT tested. - 7/ Tested with CL set at 50 pF and derated to support the indicated distributed capacitive load. capacitive derating curve. 8/ These inwts are allowed to be asvnchronws to CLK2. Thereafter guaranteed, if not tested, to the limits specified Values are either derived frm

37、characterization data or specified by design thereafter. See figure 4 for The setu, and hold swcifications are given for testing - purposes, to assure recognition within a specific CLKZ period. I I DESC FORM 193A JUL 91 Provided by IHSNot for ResaleNo reproduction or networking permitted without lic

38、ense from IHS-,-,-SMD-59b2-94533 = 9999996 0062142 Pin nunber Al A2 A3 A4 A5 A6 A7 A6 A9 A10 Al 1 A12 A13 B1 82 B3 84 85 86 87 259 = Signal name vcc vss DY V D8 D10 D12 D14 A23 A22 vcc vss vss DY 3s D6 D7 D9 D11 88 B9 D13 D15 Pin nuher 610 81 1 812 813 CI c2 c12 C13 D1 D2 D12 Dl3 El E2 E12 E13 F1 F2

39、 F12 F13 Gl G2 msIoN Signal name A2 1 vss vcc %s AS8 DY pc A18 A19 D2 D1 A17 A16 DO HLDA A15 A14 HOLD NA SHEET 9 Pin nunber GI 2 G13 Hl H2 H12 Hl3 J1 J2 JI2 J 13 K1 K2 K12 K13 L1 L2 L12 L13 Mi M2 M3 M4 Signal name A13 A12 READY CLK2 A10 Al 1 ADS BiE A8 A9 Al BHE A? A6 NC n/io A5 vcc DYE 3s WR Pin nu

40、nber M5 M6 M7 M8 M9 M10 M11 M12 M13 N1 N2 N3 N4 NS N6 N7 N8 Signal name LOCK RESET BUSY NM I INTR A2 A3 A4 vss vcc vcc vss PE, ERROR, LOCK, IO of M/IO, NA, READY and E of U/:. FIGURE 1. Terminal connections. I STANDARD1 ZED MILITARY DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 SC FOI

41、FYI 193A JUL 91 5962-94533 I Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-6 r I 9 10 11 12 Il 02 O1 O4 05 OI 07 m o) IO 11 12 Il O vss O “cc O 07C O w7 O Lot( 0000000000 0-0 9 o 9 o o o o o o WC A1 AS Rm -0 00 92 VIS Ver: Vs Vm U7D WE #LE CLU2 MA

42、ULM D1 VIS Va Vn O0 va O0 O0 mo5 D? W I L lo o O0 O2 03 O4 O1 o6 O? 88 01 10 II I2 13 - D9 D10 O0 O0 O0 Em NUI o13 014 Top Vlew vss KJtT IO 0 PERfO wsv (Component Side) Dt D12 STANDRRDI ZED MILITARY DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 O0 O0 O0 O0 O0 O0 VSf A 3s va 0000000000

43、000 0000000000000 vss - O15 AZS Va A2 All A22 Vss A4 AS A7 M AIO AI$ Al3 A17 Al8 W VeC Vp Va Vss Vm A6 A9 All Al2 Al4 Al6 A19 Ve VIS Va YUCUJMGrCOCBA SIZE 5962-94533 A RFNISIONLEVEL SHEEr 10 . 1 2 5 4 5 0000000000000 VIS Va Vn 01 DI WLM 6 CLN2 i% U Va VIS O0 Va 04 O0 44 O0 44 O0 010 4 O0 012 Dl1 Bot

44、tom View (Pln Slde) O0 nul iRa O0 nm v, O0 *i Va O0 63 “u 00000 4 A7 4 A4 Vi 00000 4 4 va Va JKLUN FIGURE 1. Terminal connections - continued. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-5962-94533 STANDARD1 ZED MILITARY DRAWING DEFENSE ELECT

45、RONICS SUPPLY CENTER DAYTON, OHIO 45444 m 9999996 0062344 021 m SI BE 5962-94533 A RJWISION SHEm 11 SEGMENTATION UNIT PREDECODE PREFLTCH DEDICATED ALU BUS 1 / 32 FIGURE 2. Functional block diagram. HOLD, INTR, NHI ERROR, BUSY RESET, HLDA - - BED-BE3 AZ-Ci31 DU-D31 ESC FORM 193A m 91 Provided by IHSN

46、ot for ResaleNo reproduction or networking permitted without license from IHS-,-,-7 SMD-5962-94533 = 9999996 0062345 Tb W CLK2 - LOCK ai-Az3 DO-Dl5 HLDA tiS ALSO APPLIES TO DATA FLOAT WHEN WRITE CYCLE IS FOLLOWED BY READ OR IDLE t14 MAX t14M MIN MAX OUTPUT FLOAT DELAY AND HLDA VALID DELAY TIMING - R

47、ESET INXTIALIZATION SEQUENCE - CLK2 RESET RESET SETUP AND HOLD TIlING AND INTERNAL PHASE FIGURE 3. Switching waveforms and test circuit. STANDARD1 ZED MILITARY DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 I SIZE I 1 5962-94533 A I I REVISIONLEVEL SHEET I I 12 DESC F?M 193A JLTL 91 Pr

48、ovided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-59b2-94533 999999b 00b2L46 T4 m STANDARD1 ZED MILITARY DRAWING DEFENSE ELECTRONICS SUPPLY CENTER - LOCK SIZE 5962-94533 A Al-A23 OUTPUT I c HLDA CLKZ OUTPUT VALID DELAY TIMING NH INfR* I SEE NOTE yw I

49、NPUT SETUP AND HOLD TtHING FIGURE 3. Switching uaveforms and test circuit - continued. I DAYTON, OHIO 45444 )FEvISIONLEvEL SHEET I 13 I I I DESC FORM 193A JUL 91 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-5962-94533 9999996 0062347 830 = CLKZ OUTPUTS (ALA