DLA SMD-5962-90858 REV A-2011 MICROCIRCUIT MEMORY DIGITAL DIGITAL CMOS 64K x 16 STATIC RANDOM ACCESS MEMORY (SRAM) MONOLITHIC SILICON.pdf

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1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Updated boilerplate for 5 year review. - lhl 11-08-24 Charles F. Saffle THE ORIGINAL FIRST SHEET OF THIS DRAWING HAS BEEN REPLACED. REV SHEET REV A A A A A SHEET 15 16 17 18 19 REV STATUS REV A A A A A A A A A A A A A A OF SHEETS SHEET 1 2 3 4 5

2、6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Kenneth Rice DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE CHECKED BY Charles Reusing APPROVED

3、BY Michael A. Frye MICROCIRCUIT, MEMORY, DIGITAL, DIGITAL, CMOS 64K x 16 STATIC RANDOM ACCESS MEMORY (SRAM), MONOLITHIC SILICON DRAWING APPROVAL DATE 91-01-29 AMSC N/A REVISION LEVEL A SIZE A CAGE CODE 67268 5962-90858 SHEET 1 OF 19 DSCC FORM 2233 APR 97 5962-E432-11 Provided by IHSNot for ResaleNo

4、reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90858 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of

5、 high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN. 1.2 P

6、IN. The PIN is as shown in the following example: 5962 - 90858 01 Q X A Federal stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2) Device class designator Case outline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 Device type(s). The device type(s) i

7、dentify the circuit function as follows: Device type Generic number Circuit function Access time 01 64K16L-100 64 x 16 CMOS SRAM Low power 100 ns 02 64K16-100 64 x 16 CMOS SRAM 100 ns 03 64K16L-85 64 x 16 CMOS SRAM Low power 85 ns 04 64K16-85 64 x 16 CMOS SRAM 85 ns 05 64K16L-70 64 x 16 CMOS SRAM Lo

8、w power 70 ns 06 64K16-70 64 x 16 CMOS SRAM 70 ns 07 64K16L-55 64 x 16 CMOS SRAM Low power 55 ns 08 64K16-55 64 x 16 CMOS SRAM 55 ns 1.2.2 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements docu

9、mentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535 1.2.3 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 a

10、nd as follows: Outline letter Descriptive designator Terminals Package style Q GDIP1-T40 or CDIP2-T40 40 dual-in-line package 1.2.4 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. Provided by IHSNot for ResaleN

11、o reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90858 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 1/ 2/ Supply voltage range - -0.5 V dc to +7.0 V dc Input v

12、oltage range - -0.5 V dc to +6.0 V dc Storage temperature range - -65C to +150C Maximum power dissipation (PD) - 1.0 W Lead temperature (soldering, 10 seconds) - +260C Thermal resistance, junction-to-case (JC): Case Q - See MIL-STD-1835 Junction temperature (TJ) - +150C 3/ 1.4 Recommended operating

13、conditions. 1/ Supply voltage range (VCC) - 4.5 V dc to 5.5 V dc Supply voltage (VSS) - 0.0 V dc Input high voltage range (VIH) - 2.2 V dc to VCC+ 0.5 V dc Input low voltage range (VIL) - -0.5 V dc to +0.8 V dc Case operating temperature range (TC) - -55C to +125C 2. APPLICABLE DOCUMENTS 2.1 Governm

14、ent specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATIO

15、N MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Mic

16、rocircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Non-Government publication

17、s. The following documents form a part of this document to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEDEC Standard No. 78 - IC Latch-Up Test. (Copies of thi

18、s document are available online at www.jedec.org/ or from JEDEC Solid State Technology Association, 3103 North 10thStreet, Suite 240-S, Arlington, VA 22201). 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing

19、 takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. _ 1/ All voltages referenced to VSS, unless otherwise specified. 2/ Stresses above the absolute maximum rating may cause permanent damage to the device. Ext

20、ended operation at the maximum levels may degrade performance and affect reliability. 3/ Maximum junction temperature shall not be exceeded except for allowable short duration burn-in screening conditions in accordance with method 5004 of MIL-STD-883. Provided by IHSNot for ResaleNo reproduction or

21、networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90858 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 4 DSCC FORM 2234 APR 97 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be

22、 in accordance with MIL-PRF-38535 as specified herein, or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for device class M shall be in accordance

23、with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and

24、 herein for device class M. 3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.4 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table(s). The truth table(s) shall be as specified on figure 2. 3.2.4 Functional tests.

25、 Various functional tests used to test this device are contained in the appendix. If the test patterns cannot be implemented due to test equipment limitations, alternate test patterns to accomplish the same results shall be allowed. For device class M, alternate test patterns shall be maintained und

26、er document revision level control by the manufacturer and shall be made available to the preparing or acquiring activity upon request. For device classes Q and V alternate test patterns shall be under the control of the device manufacturers Technology Review Board (TRB) in accordance with MIL-PRF-3

27、8535 and shall be made available to the preparing or acquiring activity upon request. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified i

28、n table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical tests for each subgroup are defined in table IIA. 3.5 Marking. The part shall be marked with the

29、PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. For RHA product using this option, the RHA desi

30、gnator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A. 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a “QML“ or “Q“

31、 as required in MIL-PRF-38535. The compliance mark for device class M shall be a “C“ as required in MIL-PRF-38535, appendix A. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requi

32、rements of this drawing (see 6.6.1 herein). For device class M, a certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6.2 herein). The certificate of compliance submitted to DLA Land and Maritime-VA prior to lis

33、ting as an approved source of supply for this drawing shall affirm that the manufacturers product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein. 3.7 Certificate of conformance. A certifi

34、cate of conformance as required for device classes Q and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change for device class M. For device class M, notification to DLA Land and M

35、aritime-VA of change of product (see 6.2 herein) involving devices acquired to this drawing is required for any change that affects this drawing. 3.9 Verification and review for device class M. For device class M, DLA Land and Maritime, DLA Land and Maritimes agent, and the acquiring activity retain

36、 the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in microcircuit

37、 group number 41 (see MIL-PRF-38535, appendix A). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90858 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 5 DSCC FORM 2234 APR 97 TABLE I.

38、Electrical performance characteristics. Test Symbol Conditions -55C TC +125C Group A Subgroups Device type Limits Unit VSS= 0 V; 4.5 V VCC 5.5 V unless otherwise specified (Test method) Min Max Output high voltage VOHIOH= -4.0 mA, VCC= 4.5 V VIL= 0.8V, VIH= 2.2 V 1, 2, 3 (3006) All 2.4 V Output low

39、voltage VOLIOL= 8.0 mA, VCC= 4.5 V VIL= 0.8V, VIH= 2.2 V 1, 2, 3 (3007) All 0.4 Input high voltage VIHVCC= 5.5 V 1, 2, 3 (3008) All 2.2 6.0 Input low voltage VILVCC= 4.5 V 1, 2, 3 (3008) All -0.5 0.8 High level input current IIHVCC= 5.5 V, VIN= 5.5 V 1, 2, 3 (3010) All 10 A Low level input current I

40、ILVCC= 5.5 V, VIN= 0.0 V 1, 2, 3 (3009) All -10 High impedance output leakage current IOZHVCC= 5.5 V, VO= 5.5 V VIL= 0.0 V, VIH= 5.0 V VIH OE VCC1, 2, 3 (3021) All 10 IOZLVCC= 5.5 V, VO= 0.0 V VIL= 0.0 V, VIH= 5.0 V VIH OE VCC1, 2, 3 (3020) -10 Operating supply current ICC1VCC= 5.5 V, CE = VILmax OE

41、 and WE = VIHf = 1/tAVAV1/ 1, 2, 3 (3005) 01, 03, 05, 07 160 mA 02, 04, 06, 08 175 Standby supply current TTL inputs ICC2VCC= 5.5 V, CE = VIHf = 0 Inputs = VIHor VIL1, 2, 3 (3005) 01, 03, 05, 07 10 02, 04, 06, 08 20 Standby supply current CMOS inputs ICC3VCC= 5.5 V, f = 0 Hz CE, UB, LB VCC-0.2 V Inp

42、uts = +0 V .2 V or VCC .2 V 1, 2, 3 (3005) All 6 Data retention current ICC4VCC= 2.0 V, f = 0 CE, UB, LB VCC-0.2 V Inputs = 0 V .2 V or VCC .2 V 1, 2, 3 (3005) 01, 03, 05, 07 1.5 Input capacitance 1/ (A0 A15) CINVIN= 0 V, tAVAV = 1.0 MHz TC = +25C, see 4.4.1e 4 (3012) All 15.0 pF Input capacitance 1

43、/ (CE, WE, OE, UB, LB) CCLKVOUT= 0 V, tAVAV= 1.0 MHz TC= +25C, see 4.4.1e 4 (3012) All 20.0 Output capacitance 1/ COUTVOUT= 0 V, tAVAV= 1.0 MHz TC= +25C, see 4.4.1e 4 (3012) All 20.0 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license f

44、rom IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90858 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics Continued. Test Symbol Conditions -55C TC +125C Group A Subgroups Device type Limits Unit VSS= 0

45、V; 4.5 V VCC 5.5 V unless otherwise specified (Test method) Min Max Functional tests See 4.4.1c 7, 8 (3014) All Read cycle time tAVAVSee figures 3 and 4, as applicable 9, 10, 11 (3003) 01, 02 100 ns 03, 04 85 05, 06 70 07, 08 55 Address access time tAVQV9, 10, 11 (3003) 01, 02 100 03, 04 85 05, 06 7

46、0 07, 08 55 Chip enable access time tELQV9, 10, 11 (3003) 01, 02 100 03, 04 85 05, 06 70 07, 08 55 Output enable to output valid tOLQV9, 10, 11 (3003) 01, 02 50 03, 04 35 05, 06 25 07, 08 20 Output hold after address change tAVQX9, 10, 11 (3003) All 5 Chip enable to output in low Z 1/ 2/ tELQX9, 10,

47、 11 (3003) All 5 Chip disable to output in high Z 1/ 2/ tEHQZ9, 10, 11 (3003) All 35 Output enable to output in low Z 1/ 2/ tOLQX9, 10, 11 (3003) All 0 Output disable to output in high Z 1/ 2/ tOHQZ9, 10, 11 (3003) All 35 Write cycle time tAVAV9, 10, 11 (3003) 01, 02 100 03, 04 85 05, 06 70 07, 08 55 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitte