DLA SMD-5962-87592 REV C-2009 MICROCIRCUITS MEMORY DIGITAL NMOS 1K x 4 HIGH-SPEED STATIC RAM MONOLITHIC SILICON.pdf

《DLA SMD-5962-87592 REV C-2009 MICROCIRCUITS MEMORY DIGITAL NMOS 1K x 4 HIGH-SPEED STATIC RAM MONOLITHIC SILICON.pdf》由会员分享，可在线阅读，更多相关《DLA SMD-5962-87592 REV C-2009 MICROCIRCUITS MEMORY DIGITAL NMOS 1K x 4 HIGH-SPEED STATIC RAM MONOLITHIC SILICON.pdf（16页珍藏版）》请在麦多课文档分享上搜索。

1、 REVISIONS LTR DESCRIPTION DATE APPROVED A Added case outline K to drawing. Changes on pages 2, 4, 9, 12, and 17. Also changes on pages 5, 6, 7, and 8. 1988 Apr 29 M. A. Frye B Updated boilerplate. Separated source bulletin from body of drawing. - glg 00-09-29 Raymond Monnin C Update drawing to curr

2、ent requirements. Editorial changes throughout. tcr 09-10-01 Charles F. Saffle THE ORIGINAL FIRST PAGE OF THIS DRAWING HAS BEEN REPLACED. CURRENT CAGE CODE 67268 REV SHEET REV C SHEET 15 REV STATUS REV C C C C C C C C C C C C C C OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY

3、James E. Jamison DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil STANDARD MICROCIRCUIT DRAWING CHECKED BY Charles Reusing THIS DRAWING IS AVAILABLE FOR USE BY All DEPARTMENTS APPROVED BY Michael. A. Frye MICROCIRCUITS, MEMORY, DIGITAL, NMOS, 1K x 4 HIGH-SPEED STATIC R

4、AM, MONOLITHIC SILICON AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 24 June 1987 AMSC N/A REVISION LEVEL C SIZE A CAGE CODE 149335962-87592 SHEET 1 OF 15 DSCC FORM 2233 APR 97 5962-E320-09 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IH

5、S-,-,-STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 SIZE A 5962-87592 REVISION LEVEL C SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance wi

6、th MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-87592 01 K A | | | | | | | | | | | | Drawing number Device type Case outline Lead finish (see 1.2.1) (see 1.2.2) (see 1.2.3) 1.2.1 Device type(s). The device type(s) shall

7、identify the circuit function as follows: Device type Generic number Circuit Access time 01 9150-25 1024 x 4 high-speed static R/W RAM 25 ns 02 9150-35 1024 x 4 high-speed static R/W RAM 35 ns 03 9150-45 1024 x 4 high-speed static R/W RAM 45 ns 1.2.2 Case outline(s). The case outline(s) are as desig

8、nated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style K GDFP2-F24 or CDFP3-F24 24 flat package L GDIP3-T24 or CDIP4-T24 24 dual-in-line package X CQCC3-N28 28 rectangular chip carrier package 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-

9、38535, appendix A. 1.3 Absolute maximum ratings. Supply voltage range -0.5 V dc to +7.0 V dc Storage temperature range . -65C to +150C Maximum power dissipation (PD): 1/ 1.2 W Lead temperature (soldering, 10 seconds) +300C Thermal resistance, junction-to-case (JC) . See MIL-STD-1835 Junction Tempera

10、ture (TJ) +175C DC output current 20 mA All signal voltages with respect to GND -3.5 V dc to +7.0 V dc 1.4 Recommended operating conditions. Case operating temperature range (TC) . -55C to +125C Maximum low level input low voltage (VIL) . 0.8 V dc Minimum high level input high voltage (VIH) . 2.2 V

11、dc Supply voltage range (VCC) 4.5 V dc minimum to 5.5 V dc maximum _ 1/ Must withstand the added PDdue to short circuit test; e.g., IOS. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLU

12、MBUS, OHIO 43218-3990 SIZE A 5962-87592 REVISION LEVEL C SHEET 3 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise sp

13、ecified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 -

14、Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/assist.daps.dla.mil/quicksearch/ or from the Standardi

15、zation Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing shall take precedence. Nothing in this document, however, supersed

16、es applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that

17、 is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval i

18、n accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to iden

19、tify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.2 Tru

20、th table. The truth table shall be as specified on figure 2. 3.2.3 Case outlines. The case outlines shall be in accordance with 1.2.2 herein. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shal

21、l apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, ap

22、pendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. Provided by IH

23、SNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 SIZE A 5962-87592 REVISION LEVEL C SHEET 4 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Con

24、ditions 1/ 2/ -55C TC +125C 4.5 V VCC 5.5 V unless otherwise specified Group A subgroups Device type Limits Unit Min Max Output high current IOHVOH= 2.4 V, VCC=4.5 V 1, 2, 3 All -4.0 mA Output low current IOLVOL= 0.4 V, VCC=4.5 V 1, 2, 3 All 12.0 mA Input high voltage VIHVCC=4.5 V to 5.5 V 1, 2, 3 A

25、ll 2.2 6.0 V Input low voltage VILVCC=4.5 V to 5.5 V 1, 2, 3 All -2.5 0.8 V Input load current IIXGND VI VCC1, 2, 3 All -10.0 10.0 A Output leakage current IOZLGND VO VCC 3/ 1, 2, 3 All -10.0 10.0 A Input capacitance CITA= 25C, VCC= 5.0 V f = 1 MHz 4/, All pins at 0 V see 4.3.1c 4 All 5 pF Output ca

26、pacitance COTA= 25C, VCC= 5.0 V f = 1 MHz 4/, All pins at 0 V see 4.3.1c 4 All 7 pF Operating supply current ICCMaximum VCC S VIL, Output open 1, 2, 3 All 180 mA Output short circuit current IOSVO= GND 4/ 5/ 1, 2, 3 All -85 -300 mA Read cycle time 6/ tAVAVSee figures 4 and 5 9, 10, 11 01 25 ns 02 35

27、 03 45 Address access time tAVQV9, 10, 11 01 25 ns 02 35 03 45 Chip select access time tELQV9, 10, 11 01 15 ns 02 20 03 25 Output enable access time tOLQV9, 10, 11 01 15 ns 02 20 03 25 Chip select low to output in low Z 4/ 7/ tELQX9, 10, 11 All 0 ns Chip select high to output in high Z 4/ 7/ tEHQZ9,

28、 10, 11 01 0 20 ns 02 0 25 03 0 30 Output enable low to output in low Z 4/ 7/ tOLQX9, 10, 11 All 0 ns Output enable high to output in high Z 4/ 7/ tOHQZ9, 10, 11 01 0 20 ns 02 0 25 03 0 30 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without lic

29、ense from IHS-,-,-STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 SIZE A 5962-87592 REVISION LEVEL C SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - continued. Test Symbol Conditions 1/ 2/ -55C TC +125C 4.5 V VCC 5.5 V unless oth

30、erwise specified Group A subgroups Device type Limits Unit Min Max Output hold after Address change tAXQXSee figures 4 and 5 9, 10, 11 All 1 ns Write cycle time 8/ tWC9, 10, 11 01 25 ns 02 35 03 45 Chip select low to write enable high tELWH9, 10, 11 01 15 ns 02 20 03 30 Address valid to end of write

31、 tAVWH9, 10, 11 01 20 ns 02 30 03 40 Address valid to beginning of write tAVWL9, 10, 11 All 5 ns Write pulse width tWLWH9, 10, 11 01 15 ns 02 20 03 30 Address hold after end of write tWHAX9, 10, 11 All 5 ns Data in valid to write enable high tDVWH9, 10, 11 01 15 ns 02 20 03 30 Data hold after end of

32、 write tWHDX9, 10, 11 All 5 ns Write enable low to output in high Z 4/ tWLQZ9, 10, 11 01 0 20 ns 02 0 25 03 0 30 Write enable high to output in low Z 4/ tWHQX9, 10, 11 All 0 ns Reset cycle time tRRC9, 10, 11 01 50 ns 02 70 03 90 Address valid to beginning of reset tAVRL9, 10, 11 All 0 ns Write enabl

33、e high to beginning of reset tWHRL9, 10, 11 All 0 ns Chip select low to beginning of reset tELRL9, 10, 11 All 0 ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLU

34、MBUS COLUMBUS, OHIO 43218-3990 SIZE A 5962-87592 REVISION LEVEL C SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - continued. Test Symbol Conditions 1/ 2/ -55C TC +125C 4.5 V VCC 5.5 V unless otherwise specified Group A subgroups Device type Limits Unit Min Max Reset p

35、ulse width tRLRHSee figures 4 and 5 9, 10, 11 01 20 ns 02 30 03 40 Chip select hold after end of reset tRHEX9, 10, 11 All 0 ns Write enable hold after end of reset tRHWL9, 10, 11 01 30 ns 02 40 03 50 Address hold after end of reset tRHAX9, 10, 11 01 30 ns 02 40 03 50 Reset low to output in high Z 4/

36、 7/ tRLQZ9, 10, 11 01 0 20 ns 02 0 25 03 0 30 Reset high to output in low Z 4/ 7/ tRHQX9, 10, 11 All 0 ns 1/ Test conditions assume signal transition times of 10 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V and output loading of the specific IOL/IOHand 30 pF load ca

37、pacitance (see figure 4A). Output timing reference is 1.5 V. 2/ The operating case temperature range is guaranteed with transverse air flow of 400 linear feet per minute. 3/ Output is in tri-state. 4/ Not tested, guaranteed parameter. 5/ For test purposes, not more than one output at a time should b

38、e shorted. Short circuit test duration should not exceed 30 seconds. 6/ W and R are high for read cycle. 7/ Transition is measured at + 500 mV from steady state voltage with specified loading shown in figure 4B. 8/ The internal write time of the memory is defined by the overlap of S low and W low. B

39、oth signals must be low to initiate a write and either signal can terminate a write by going high. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the write. R must be high. Provided by IHSNot for ResaleNo reproduction or networking permitte

40、d without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 SIZE A 5962-87592 REVISION LEVEL C SHEET 7 DSCC FORM 2234 APR 97 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compl

41、iance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in

42、 order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requiremen

43、ts herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DSCC-VA shall be required for any change that affects thi

44、s drawing. 3.9 Verification and review. DSCC, DSCCs agent and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 4. VERIFICATION 4.1 Sampling and in

45、spection. Sampling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening. Screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection. The following additional criteria shall

46、apply: a. Burn-in test, method 1015 of MIL-STD-883. (1) Test condition C or D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or procuring activity upon request. The test circuit shall specify the inputs, ou

47、tputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015 of MIL-STD-883. (2) TA= +125C, minimum. b. Interim and final electrical test parameters shall be as specified in table II herein, except interim electrical parameter tests prior to burn-in are optional at the discretion of the manufacturer. 4.3 Quality conformance inspection. Quality conformance inspection shall be in accordance with method 5005 of MIL-STD-883 including grou