DLA SMD-5962-87591 REV D-2013 MICROCIRCUIT LINEAR HIGH SPEED ANALOG TO DIGITAL CONVERTER MONOLITHIC SILICON.pdf

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1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Correct title to read ANALOG TO DIGITAL. Change conditions for timing tests, table I. Change figure 3. Editorial changes throughout. 90-01-24 M. A. Frye B Changes in accordance with NOR 5962-R231-94. 94-08-12 M. A. Frye C Update drawing to curren

2、t requirements. Editorial changes throughout. - gap 01-08-30 Raymond Monnin D Redrawn. Paragraphs updated to MIL-PRF-38535 requirements. -drw 13-01-25 Charles F. Saffle THE ORIGINAL FIRST SHEET OF THIS DRAWING HAS BEEN REPLACED. REV SHEET REV SHEET REV STATUS REV D D D D D D D D D D D D D OF SHEETS

3、SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 PMIC N/A PREPARED BY Joseph A. Kerby DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE CHECKED BY Charles E

4、. Besore APPROVED BY Michael A. Frye MICROCIRCUIT, LINEAR, HIGH SPEED, ANALOG TO DIGITAL CONVERTER, MONOLITHIC SILICON DRAWING APPROVAL DATE 87-08-18 AMSC N/A REVISION LEVEL D SIZE A CAGE CODE 67268 5962-87591 SHEET 1 OF 13 DSCC FORM 2233 APR 97 5962-E217-13 Provided by IHSNot for ResaleNo reproduct

5、ion or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87591 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN cl

6、ass level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-87591 01 L A Drawing number Device type (see 1.2.1) Case outline (see 1.2.2) Lead finish (see 1.2.3) 1.2.1 Device types. The devic

7、e types identify the circuit function as follows: Device type Generic number Circuit function 01 AD7572 12.5-microsecond, 11-bit linearity, 12-bit resolution CMOS A/D converter with 45 ppm/C reference. 02 AD7572 12.5-microsecond, 11-bit linearity, 12-bit resolution CMOS A/D converter with 25 ppm/C r

8、eference. 03 AD7572 12.5-microsecond, 12-bit linearity, 12-bit resolution CMOS A/D converter with 25 ppm/C reference. 04 AD7572 5-microsecond, 11-bit linearity, 12-bit resolution CMOS A/D converter with 45 ppm/C reference. 05 AD7572 5-microsecond, 11-bit linearity, 12-bit resolution CMOS A/D convert

9、er with 25 ppm/C reference. 06 AD7572 5-microsecond, 12-bit linearity, 12-bit resolution CMOS A/D converter with 25 ppm/C reference. 1.2.2 Case outlines. The case outlines are as designated in MIL-STD-1835 as follows: Outline letter Descriptive designator Terminals Package style L GDIP3-T24 or CDIP4

10、-T24 24 Dual-in-line 3 CQCC1-N28 28 Leadless square chip carrier 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87591 DLA LAND

11、 AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. (TA = +25C, unless otherwise noted). VDDto DGND . -0.3 V dc to +7 V dc VSSto DGND . +0.3 V dc to -17 V dc AGND to DGND . -0.3 V dc, VDD+0.3 V dc AINto AGND -15 V dc to +15 V dc Digita

12、l input voltage to DGND -0.3 V dc, VDD+0.3 V dc Digital output voltage to DGND . -0.3 V dc, VDD+0.3 V dc Storage temperature range . -65C to +150C Power dissipation +75C 1,000 mW 1/ Thermal resistance (JC) See MIL-STD-1835 Junction temperature (TJ) +175C 1.4 Recommended operating conditions. Operati

13、ng voltage range: Positive supply (VDD) +4.75 V dc to +5.25 V dc Negative supply (VSS) . -14.25 V dc to -15.75 V dc Clock frequency (fCLK) 1.0 MHz for device types 01, 02, and 03 2.5 MHz for device types 04, 05, and 06 Analog input voltage range (AIN) (specifications apply to slow memory mode) . 0 t

14、o +5.0 V dc Ambient operating temperature range (TA) -55C to +125C 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues

15、of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard E

16、lectronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.dla.mil/quicksearch/ or from the Standardization Document Order De

17、sk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regula

18、tions unless a specific exemption has been obtained. _ 1/ Derate power dissipation above +75C by 10 mW/C. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87591 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990

19、REVISION LEVEL D SHEET 4 DSCC FORM 2234 APR 97 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufa

20、cturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. T

21、his QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordan

22、ce with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outlines. The case outlines shall be in accor

23、dance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Load circuits. The load circuits shall be as specified on figures 2 and 3. 3.2.4 Timing diagrams. The timing diagrams shall be as specified on figures 4, 5, 6, and 7. 3.3 Electrical

24、 performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full ambient operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specifi

25、ed in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking o

26、f the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The

27、 compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved sour

28、ce of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DLA Land and Maritime -VA prior to listing as an approved source of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certif

29、icate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DLA Land and Maritime -VA shall be required for any change that affects this d

30、rawing. 3.9 Verification and review. DLA Land and Maritime, DLA Land and Maritimes agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. Pro

31、vided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87591 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol C

32、onditions -55C TA +125C Device types Group A subgroups Limits Unit unless otherwise specified Min Max Integral linearity error LE VDD= 5 V, VSS= -15 V 01, 02, 1 1 LSB 04, 05 2, 3 1 03, 06 2, 3 3/4 03, 06 12 1/2 Differential linearity error DLE VDD= 5 V, VSS= -15 V All 1, 2, 3 1 Offset error VOSVDD=

33、5 V, VSS= -15 V All 1 4 LSB 01, 04 2, 3 6 02, 05 2, 3 5 03, 06 2, 3 4 02, 03, 05, 06 12 3 Full scale error including internal voltage reference error, (Ideal last code transition = FS-3/2LSBs) AE VDD= 5 V All 1 15 LSB VSS= -15 V, Full scale = 5 V 02, 03, 05, 06 12 10 Full scale temperature coefficie

34、nt, including internal voltage reference drift dAE/dT VDD= 5 V 01, 04 2, 3 45 ppm/C VSS= -15 V 02, 03, 05, 06 25 Analog input current IINAIN= 5 V All 1, 2, 3 3.5 mA Internal reference voltage output VREFVDD= 5 V, VSS= -15 V All 1 -5.3 -5.2 V Internal reference output current sink capability Constant

35、 external load during conversion All 13, 14, 15 550 A Digital input low voltage VINLCS, RD, HBEN, CLK IN. VDD= 4.75 V All 1, 2, 3 0.8 V Digital input high voltage VINHVSS= -15 V All 1, 2, 3 2.4 Digital input capacitance CINAll 13 10 pF Digital input current IINCS, RD, HBEN. VDD= 5 .25 V, VSS= -15 V,

36、 AIN= 0 to VDDAll 1, 2, 3 10 A CLK IN. VDD= 5.25 V, VSS= -15 V, AIN= 0 to VDDAll 20 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87591 DLA LAND AND MARITIME COLUMBUS, OHIO 43

37、218-3990 REVISION LEVEL D SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - continued. Test Symbol Conditions -55C TA +125C Device types Group A subgroups Limits Unit unless otherwise specified Min Max Digital output low voltage VOLD11-D0/8, BUSY, CLK OUT VDD= 4.75 V, V

38、SS= -15 V, All 1, 2, 3 0.4 V Digital output high voltage VOHIsink = 1.6 mA, Isource = 200 A All 1, 2, 3 4.0 Floating state leakage current VOLD11-D0/8. VDD= 5.25 V, VSS= -15 V All 1, 2, 3 10 A Floating state output capacitance COUTAll 13, 14, 15 15 pF Conversion time using synchronous clock tCONV04,

39、 05, 06 13, 14, 15 5 s 01, 02, 03 12.5 Conversion time using asynchronous clock 1/ tCONV04, 05, 06 9, 10, 11 4.8 5.2 01, 02, 03 12.0 13.0 Power supply current from VDDIDDVDD= 5.25 V, VSS= -15.75 V All 1, 2, 3 7 mA Power supply current from VSSISSCS = RD = BUSY = HIGH AIN= 5 V All 1, 2, 3 12 CS to RD

40、 setup time t1See figures 4, 5, 6, and 7 2/ All 9, 14, 15 0 ns RD to BUSY t2All 9 190 propagation delay 14, 15 270 Data access time after t33/ All 9 110 RD , CL = 60 pF (see figure 2) 4/ 14, 15 150 Data access time after t33/ All 9 125 RD , CL = 100 pF (see figure 2) 14, 15 170 RD pulse width t4All

41、9, 14, 15 t3CS to RD hold time t5All 9, 14, 15 0 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87591 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 7 D

42、SCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - continued. Test Symbol Conditions -55C TA +125C Device types Group A subgroups Limits Unit unless otherwise specified Min Max Data setup time after t63/ See figures 4, 5, 6, and 7 2/ All 9 70 ns BUSY , CL= 60 pF (see figure 2) 14

43、, 15 100 Bus relinquish time t75/ All 9 35 90 (see figure 3) 14, 15 20 90 HBEN to RD setup time t8All 9, 14, 15 0 HBEN to RD hold time t9All 9, 14, 15 0 Delay between successive read operations t10All 9, 14, 15 500 1/ Conversion time using asynchronous clock is measured by setting the clock frequenc

44、y at the appropriate value (see 1.4) and checking all remaining tested specifications. 2/ All input control signals are specified with tr= tf= 5 ns (10 percent to 90 percent of +5 V) and timed from a voltage level of 1.6 V. Time t6and t10are measured only for the initial test and after process or de

45、sign changes which may affect switching parameters. 3/ Time t3and t6are measured with the load circuits of figure 2 and defined as the time required for an output to cross 0.8 V or 2.4 V. 4/ If not tested, shall be guaranteed to the limits specified in table I herein. 5/ Time t7is defined as the tim

46、e required for the data lines to change 0.5 V when loaded with the circuits of figure 3. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87591 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D

47、SHEET 8 DSCC FORM 2234 APR 97 Device type ALL Case outline L 3 Terminal number Terminal symbol 1 AIN NC 2 VREF AIN 3 AGND VREF 4 D11 AGND 5 D10 D11 6 D9 D10 7 D8 D9 8 D7 NC 9 D6 D8 10 D5 D7 11 D4 D6 12 DGND D5 13 D3/11 D4 14 D2/10 DGND 15 D1/9 NC 16 D0/8 D3/11 17 CLK IN D2/10 18 CLK OUT D1/9 19 HBEN

48、 D0/8 20 RD CLK IN 21 CS CLK OUT 22 BUSY NC 23 VSS HBEN 24 VDD RD 25 - - - CS 26 - - - BUSY 27 - - - VSS 28 - - - VDD NC = no connect FIGURE 1. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87591 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 9 DSCC FORM 2234 APR 97 FIGURE 2. Load circuit for access time. FIGURE 3