DLA SMD-5962-10233 REV A-2012 MICROCIRCUIT LINEAR RADIATION HARDENED CMOS 16 TO 1 ANALOG MULTIPLEXER MONOLITHIC SILICON.pdf

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1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Add device types 03 and 04. Remove class M requirements. - drw 12-08-21 Charles F. Saffle REV SHEET REV A A A A A A A A A SHEET 15 16 17 18 19 20 21 22 23 REV STATUS REV A A A A A A A A A A A A A A OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14

2、 PMIC N/A PREPARED BY Dan Wonnell DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE CHECKED BY Rajesh Pithadia APPROVED BY Charles F. Saffle MI

3、CROCIRCUIT, LINEAR, RADIATION HARDENED, CMOS, 16 TO 1 ANALOG MULTIPLEXER, MONOLITHIC SILICON DRAWING APPROVAL DATE 12-01-09 AMSC N/A REVISION LEVEL A SIZE A CAGE CODE 67268 5962-10233 SHEET 1 OF 23 DSCC FORM 2233 APR 97 5962-E450-12 Provided by IHSNot for ResaleNo reproduction or networking permitte

4、d without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-10233 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device class Q)

5、and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN. 1.2 PIN. The PIN is as shown in the following ex

6、ample: 5962 F 10233 01 Q X C Federal stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2) Device class designator Case outline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-3853

7、5 specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device types. The device types identify the circuit function as follows: Device type Generic number Circuit function 01 UT16MX110 Radiation hardened, CMOS 16 channel MUX, asynchron

8、ous parallel address interface 02 UT16MX110 Radiation hardened, CMOS 16 channel MUX, asynchronous parallel address interface with additional screening 1/ 03 UT16MX111 Radiation hardened, CMOS 16 channel MUX, synchronous parallel address interface 04 UT16MX112 Radiation hardened, CMOS 16 channel MUX,

9、 serial address interface 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements documentation Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline. The case outline is a

10、s designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style X See figure 1 28 Flat pack 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V. _ 1/ Device type 02 provides a QML-Q product with the additional test

11、ing as specified in section 4.2.1.d herein. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-10233 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute ma

12、ximum ratings. 1/ Supply voltage between AVDDand AVSS. 7.8 V Power dissipation 150 mW Junction temperature (TJ) range . -55C to +130C Storage temperature (TSTG) range -65C to +150C ESDHBM 2kV 2/ Thermal resistance, junction -to-case (JC) 4.8C/W 1.4 Recommended operating conditions. Analog positive s

13、upply voltage (AVDD) 4.5 V to 5.5 V Analog negative supply voltage (AVSS) . 0 V Analog input voltage (VIN) . AVSSto AVDDDigital input voltage (VI) 0 V to 3.6 V Case operating temperature range (TC) -55C to +125C Junction temperature operating range (TJ) . -55C to +130C 1.5 Radiation features. Maximu

14、m total dose available (dose rate = 50 300 rads(Si)/s) 3 x 105rads(Si) 3/ Single event phenomenon (SEP): Effective linear energy transfer (LET), no upsets . 62.3 MeV-cm2/mg 4/ Effective linear energy transfer (LET), no latch-up 110 MeV-cm2/mg 4/ 2. APPLICABLE DOCUMENTS 2.1 Government specification,

15、standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - I

16、ntegrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings.

17、 MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) _ 1/ Stresses above the absolute maximum rating may ca

18、use permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2/ Test per MIL-STD-883, Method 3015.7. 3/ Radiation end point limits for the noted parameters are guaranteed only for the conditions as specified in MIL-STD-883, method 1019,

19、 condition A. 4/ Limits are guaranteed by design or process, but not production tested unless specified by the customer through the purchase order or contract. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-

20、10233 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 4 DSCC FORM 2234 APR 97 2.2 Non-Government publications. The following document form a part of this document to the extent specified herein. Unless otherwise specified, the issues of the documents are the issues of the docu

21、ments cited in the solicitation or contract. ASTM INTERNATIOINAL (ASTM) ASTM F1192 - Standard Guide for the Measurement of Single Event Phenomena (SEP) induced by Heavy Ion Irradiation of Semiconductor Devices (Copies of this document are available online at http:/ www.astm.org/ or from ASTM Interna

22、tional, 100 Barr Harbor Drive, P.O. Box C700, West Conshohocken, PA 19428-2959.) 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable l

23、aws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturers Quality Management (QM) p

24、lan. The modification in the QM plan shall not affect the form, fit, or function as described herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V. 3.2.1 Case outline.

25、 The case outline shall be in accordance with 1.2.4 herein and figure 1. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2. 3.2.3 Truth tables. The truth tables shall be as specified on figure 3 and figure 4. 3.2.4 Block diagram. The block diagram shall be as spe

26、cified on figure 11. 3.2.5 Radiation exposure circuit. The radiation exposure circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing and acquiring activity upon request. 3.3 Electrical performance characteristics and postirr

27、adiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table IA and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirement

28、s shall be the subgroups specified in table IIA. The electrical tests for each subgroup are defined in table IA. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is

29、not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. 3.5.1 Certification/compliance m

30、ark. The certification mark for device classes Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this dr

31、awing (see 6.6.1 herein). The certificate of compliance submitted to DLA Land and Maritime-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturers product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein. 3.7 Certificate

32、 of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 shall be provided with each lot of microcircuits delivered to this drawing. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DR

33、AWING SIZE A 5962-10233 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 5 DSCC FORM 2234 APR 97 TABLE IA. Electrical performance characteristics. 1/, 2/ Test Symbol Conditions -55C TC +125C AVDD= 5.0 V0.5 V, AVSS= 0 V, GND = 0 V Group A subgroups Device type Limits Unit unless

34、 otherwise specified Min Max DC Electrical Characteristics Digital input low VIL1, 2, 3 All -0.3 0.8 V Digital input high VIH1, 2, 3 All 2.0 3.6 V Digital output low VOLIOL = 100A 1, 2, 3 04 0.2 V IOL= 2mA 0.4 Digital output high VOHIOH= -100A 1, 2, 3 04 2.8 V IOH= -2mA 2.4 On resistance RONVIN= AVS

35、Sto AVDD, VCOM= VIN- 0.3 V 1, 2, 3 All 40 300 Functional tests See 4.4.1b 7, 8A, 8B All Analog I/O leakage current (switch off) 3/ IOFFAVDD= 5.5 V, VIN= AVSSto AVDD 1, 2, 3 All -1.6 1.6 A Digital input current low IILAVDD= 5.5 V, VIL= GND LVCMOS/CMOS inputs 1, 2, 3 All -1.0 A Inputs with pull-up -38

36、0 Inputs with pull-down 03 -5.0 Digital input current high IIHAVDD= 4.5 V, VIH= 3.6 V LVCMOS/CMOS inputs 1, 2, 3 All 300 A Inputs with pull-up 4/ 300 Inputs with pull-down 03 200 AVDD= 5.5 V, VIH= 3.0 V LVCMOS/CMOS inputs 1, 2, 3 All 1.0 A Inputs with pull-up 4/ -50 Inputs with pull-down 03 100 Quie

37、scent analog supply current QIDDAVDD= 5.5 V, VIH= 3.3 V, VIL= GND 1, 2, 3 All 3.0 mA See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-10233 DLA LAND AND MARITIME COLUMBUS, OHIO 4

38、3218-3990 REVISION LEVEL A SHEET 6 DSCC FORM 2234 APR 97 TABLE IA. Electrical performance characteristics - continued. 1/, 2/ Test Symbol Conditions -55C TC +125C AVDD= 5.0 V0.5 V, AVSS= 0 V, GND = 0 V Group A subgroups Device type Limits Unit unless otherwise specified Min Max AC Electrical Charact

39、eristics Input analog capacitance (switch off) 5/, 6/ CINFIN= 1 MHz 0 V, See 4.4.1d4 All 50 pF Input digital capacitance 5/, 6/ CIN_ DIGITALFIN= 1 MHz 0 V, See 4.4.1d4 All 55 pF Output capacitance at COM 5/, 6/ COUTFIN= 1 MHz 0 V, See 4.4.1d4 All 80 pF Off isolation, feed through attenuation (switch

40、 off) 5/, 7/ OISORL= 600, CL= 50 pF, FIN= 1 kHz sine wave, See 4.4.1d 4 All -80 dB Bandwidth (frequency response) 5/, 7/ BW RL= 50, CL= 10 pF, VI= 1 Vp-p, See 4.4.1d 4 All 51 MHz Cross talk (between any 2 channels) 5/, 7/ XTALK2RL= 1 k, CL= 50 pF, FIN= 1 kHz sine wave, See 4.4.1d 4 All -80 dB Settli

41、ng time of output at COM within 1% of final output voltage 5/, 7/ tSRL= 100 k, CL= 50 pF 9 All 120 ns Total harmonic distortion 5/, 7/ THD RL= 1 k, CL= 50 pF, See 4.4.1d FIN= 1 MHz sine wave, VIN= 5 Vp-p4 All 5.0 % Timing Characteristics Propagation delay of analog signal input (Sx to analog output

42、(COM) measured at 50%. 5/ tPROP_SRT= 50, CL= 50 pF, See figures 10 and 13 9, 10, 11 All 25 ns Propagation delay of any changes in the digital inputs (A3:0, CS/, PLATCH, SS/) affecting the analog output (COM). 5/ tPROP_DRT= 50, CL= 50 pF See figure 5 and 13 9, 10, 11 01, 02 25 140 ns See figure 6 and

43、 13 03 25 140 See figure 7 and 13 04 25 140 Mux decoding time 5/ tMUXRT= 50, CL= 50 pF See figure 5 and 13 9, 10, 11 01, 02 50 ns See figure 6 and 13 03 50 See figure 7 and 13 04 50 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license fr

44、om IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-10233 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 7 DSCC FORM 2234 APR 97 TABLE IA. Electrical performance characteristics - continued. 1/, 2/ Test Symbol Conditions -55C TC +125C AVDD= 5.0 V0.5 V, AVSS= 0 V, GND = 0 V G

45、roup A subgroups Device type Limits Unit unless otherwise specified Min Max Timing Characteristics - continued Break-Before-Make-Delay 5/ tBBMRT= 50, CL= 50 pF See figure 5 and 13 9, 10, 11 01, 02 15 90 ns See figure 6 and 13 03 15 90 See figure 7 and 13 04 15 90 Output enable time from HiZ to low o

46、r high once RESET/ is pulled high 5/ tPZLHRT= 50, CL= 50 pF See figure 9 and 13 9, 10, 11 03, 04 90 ns Output disable time from low or high to HiZ once RESET/ is pulled low 5/ tPLHZRT= 50, CL= 50 pF See figure 9 and 13 9, 10, 11 03, 04 55 ns SCLK frequency 5/ fSCLKSee figure 7 9, 10, 11 04 2.0 MHz S

47、CLK high time 5/ tHSee figure 7 9, 10, 11 04 190 ns SCLK low time 5/ tLSee figure 7 9, 10, 11 04 190 ns First SCLK setup time (for shifting window) 5/ tSSUSee figure 7 9, 10, 11 04 6.0 ns Last SCLK hold time (for shifting window) 5/ tSSHSee figure 7 9, 10, 11 04 10 ns Data in (MOSI) setup time wrt r

48、ising edge SCLK 5/ tSUSee figure 7 9, 10, 11 04 3.0 ns Data in (MOSI) hold time wrt rising edge SCLK 5/ tHDSee figure 7 9, 10, 11 04 5.0 ns Data out (MISO) valid (after falling edge of SCLK) 5/ tDOCL= 50 pF, See figure 7 9, 10, 11 04 43 ns Data out (MISO) rise time 5/ tDR10 - 90% 3V_OUT, CL= 50 pF 9, 10, 11 04 30 ns Data out (MISO) fall time 5/ tDF10 - 90% 3V_OUT, CL = 50 pF 9,