DLA SMD-5962-10230 REV A-2013 MICROCIRCUIT MEMORY DIGITAL CMOS 16-MEG X 48-BIT X 4-BANK (3-GIG) RADIATION-HARDENED SYNCHRONOUS DRAM (SDRAM) MULTICHIP MODULE.pdf

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1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Add case outline Y. Correction to tLZin Table IA. Corrections to tACheader lines in timing diagrams. - glg 13-03-26 Charles Saffle REV A A A A A A SHEET 55 56 57 58 59 60 REV A A A A A A A A A A A A A A A A A A A A SHEET 35 36 37 38 39 40 41 42 4

2、3 44 45 46 47 48 49 50 51 52 53 54 REV A A A A A A A A A A A A A A A A A A A A SHEET 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 REV STATUS REV A A A A A A A A A A A A A A OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Gary L. Gross DLA LAND AND MARITIME COLUMB

3、US, OHIO 43218-3990 http:/www.landandmaritime.dla.mil STANDARD MICROCIRCUIT DRAWING CHECKED BY Laura Leeper THIS DRAWING IS AVAILABLE FOR USE BY All DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE APPROVED BY Charles F. Saffle MICROCIRCUIT, MEMORY, DIGITAL, CMOS, 16-MEG X 48-BIT X 4-BANK (3-GI

4、G), RADIATION-HARDENED, SYNCHRONOUS DRAM (SDRAM), MULTICHIP MODULE DRAWING APPROVAL DATE 12-09-06 AMSC N/A REVISION LEVEL A SIZE A CAGE CODE 67268 5962-10230 SHEET 1 OF 60 DSCC FORM 2233 APR 97 5962-E289-13 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS

5、-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-10230 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device class Q) and space application (dev

6、ice class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. 1.2 PIN. The PIN shall be as shown in the following example: 5962 R 10230

7、 01 Q X A Federal RHA Device Device Case Lead stock class designator type class outline finish designator (see 1.2.1) (see 1.2.2) designator (see 1.2.4) (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices shall meet the MIL-PRF-38535 specified R

8、HA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device types. The device types shall identify the circuit function as follows: Device type Generic number Circuit function Access time 01 8SDMQ64M48 16M X 48-bit X 4-bank SDRAM 7.5 ns 02 8SDMQ6

9、4M48 16M X 48-bit X 4-bank SDRAM, with additional screening 1/ 7.5 ns 1.2.3 Device class designator. The device class designator shall be a single letter identifying the product assurance level as follows: Device class Device requirements documentation Q, V Certification and qualification to MIL-PRF

10、-38535 1.2.4 Case outline(s). The case outline(s) shall be as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style X See figure 1 128 dual cavity quad flat pack Y See figure 1 128 dual cavity quad flat pack 1.2.5 Lead finish. The lead finish shall

11、be as specified in MIL-PRF-38535 for classes Q and V. 1.3 Absolute maximum ratings. 2/ 3/ Supply voltage range, (VDD,VDDQ) -1.0 V dc to +4.3 V dc Voltage range on any pin relative to ground -0.3 V dc to VDD+0.3 V dc Power dissipation permitted, PD TC= 105C 4.0 W Storage temperature range, (TSTG) -65

12、C to +150C Junction temperature, (TJ) . +125C Thermal resistance, junction-to-case, (JC): Case X 5C/W 1.4 Recommended operating conditions. Positive supply voltage, (VDD,VDDQ) . +3.0 V dc to +3.6 V dc Input voltage, dc 0 V dc to VDDQCase operating temperature range, (TC) -40C to +105C 1/ Device type

13、 02 provides QML Q product with additional testing as specified in paragraph 4.2.1d. 2/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 3/ All voltage values in this drawing

14、are with respect to VSS. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-10230 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 3 DSCC FORM 2234 APR 97 1.5 Radiation features Maximum tot

15、al dose available (dose rate = 50 - 300 rads(Si)/s) 100 krads(Si) 5/ Single event phenomenon (SEP): No SEU occurs at effective LET (see 4.4.4.2) . 0.8 MeV-cm2/mg 6/ No SEL occurs at effective LET (see 4.4.4.2) . 111 MeV-cm2/mg (SEU event rate = 1.3 x 10-10events/bit-day with cross section 7.6 x 10-1

16、0cm2/bit). 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation o

17、r contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE

18、 HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19

19、111-5094.) 2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein. Unless otherwise specified, the issues of the documents are the issues of the documents cited in the solicitation. AMERICAN SOCIETY FOR TESTING AND MATERIALS (ASTM) ASTM

20、 Standard F1192 - Standard Guide for the Measurement of Single Event Phenomena (SEP) Induced by Heavy Ion Irradiation of Semiconductor Devices. (Applications for copies of ASTM publications should be addressed to: ASTM International, PO Box C700, 100 Barr Harbor Drive, West Conshohocken, PA 19428-29

21、59; http:/www.astm.org.) JEDEC INTERNATIONAL (JEDEC) JEDEC Standard Number 78 - IC Latch-Up Test. (Applications for copies should be addressed to the Electronics Industries Association, 2500 Wilson Boulevard, Arlington, VA 22201; http:/www.jedec.org.) (Non-Government standards and other publications

22、 are normally available from the organizations that prepare or distribute the documents. These documents also may be available in or through libraries or other informational services.) 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herei

23、n, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. _ 5/ Device is irradiated in accordance with MIL-STD-883, method 1019, condition A, and is guaranteed to a maximum total dose spe

24、cified herein. 6/ Assuming geosynchronous orbit and Adams 90% worst environment (based on Space Radiation 5.0). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-10230 DLA LAND AND MARITIME COLUMBUS, OHIO 43218

25、-3990 REVISION LEVEL A SHEET 4 DSCC FORM 2234 APR 97 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturers Quality Management (QM) plan. The modif

26、ication in the QM plan shall not affect the form, fit, or function as described herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V. 3.2.1 Case outline(s). The case o

27、utline(s) shall be in accordance with 1.2.4 herein and figure 1. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2. 3.2.3 Truth table(s). The truth table(s) shall be as specified on figure 3. 3.2.4 Output load circuit. The output load circuit shall be as specifie

28、d on figure 4. 3.2.5 Timing waveforms. The timing waveforms shall be as specified on figure 5. 3.2.6 Radiation test circuit. The radiation test circuit shall be maintained under document revision level control by the manufacturer and shall be made available to the preparing or acquiring activity upo

29、n request. 3.2.7 Functional tests. Various functional tests used to test this device are contained herein. If the test patterns cannot be implemented due to test equipment limitations, alternate test patterns to accomplish the same results shall be allowed. For device classes Q and V, alternate test

30、 patterns shall be under the control of the device manufacturers Technology Review Board (TRB) in accordance with MIL-PRF-38535 and shall be made available to the preparing or acquiring activity upon request. 3.3 Electrical performance characteristics and post-irradiation parameter limits. Unless ot

31、herwise specified herein, the electrical performance characteristics and post-irradiation parameter limits are as specified in Table IA and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified

32、in Table IIA. The electrical tests for each subgroup are defined in Table IA. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitatio

33、ns, the manufacturer has the option of not marking the “5962-“ on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. 3.5.1 Certification/compliance mark. The certification mark for dev

34、ice classes Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For devic

35、e class M, a certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6.2 herein). The certificate of compliance submitted to DLA Land and Maritime-VA prior to listing as an approved source of supply for this drawing

36、 shall affirm that the manufacturers product meets, for device classes Q and V. 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits del

37、ivered to this drawing. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-10230 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 5 DSCC FORM 2234 APR 97 TABLE IA. Electrical performance ch

38、aracteristics. Test Symbol Test conditions 1/ 2/ -40C TC +105C +3.0 V VDD +3.6 V Unless otherwise specified all voltages referenced to VSS Group A subgroups Device type Limits Unit Min Max High-level input voltage 3/ 4/ VIH1,2,3 All 2.2 V Low-level input voltage 3/ 4/ VIL1,2,3 All 0.6 V High-level o

39、utput voltage 3/ 4/ VOHIOH = -4 mA 1,2,3 All 2.4 V Low-level output voltage 3/ 4/ VOLIOL = 4 mA 1,2,3 All 0.4 V Input capacitance 5/ CINf = 1 MHz 0 V see 4.4.1e 4 All 75 pF Bidirectional I/O capacitance 5/ CIO4 All 25 pF Input leakage current 3/ 4/ IIN0 V VlN = VDD1,2,3 All -5 5 A Output leakage cur

40、rent 3/ 4/ IOZ0 V VOUT = VDDQ DQs are disabled 1,2,3 All -5 5 A Operating current, active mode 3/ 4/ 6/ 7/ 8/ 9/ 10/ 11/ IDD1CK = 100 MHz, Burst = 2, READ or WRITE, tRC= tRC(min) 1,2,3 All 450 mA Standby current, power-down mode 3/ 4/ 7/ 8/ 11/ IDD2CK = 100 MHz, CKE = LOW, All banks idle 1,2,3 All 1

41、5 mA Standby current, active mode 3/ 4/ 6/ 7/ 8/ 10/ 11/ 12/ IDD3CK = 100 MHz, CS = HIGH, CKE = HIGH, All banks active after tRCDmet, No accesses in progress 1,2,3 All 165 mA Operating current: Burst mode , Page burst 3/ 4/ 6/ 7/ 8/ 9/ 10/ 11/ IDD4READ or WRITE, All banks active 1,2,3 All 450 mA Aut

42、o refresh current 3/ 4/ 6/ 7/ 8/ 9/ 10/ 11/ 13/ IDD5CS = HIGH, CKE = HIGH tRFC= tRFC(min) 1,2,3 All 1150 mA IDD6tRC = 3.9 s 1,2,3 All 150 mA Functional test See 4.4.1c, TC= 25C 7, 8A, 8B All AC Characteristics 3/ 4/ 7/ 14/ 15/ 16/ Access time from CLK tAC(3)See figures 4 and 5 as applicable, Positiv

43、e edge (CL = 3) 9,10,11 All 7.5 ns Access time from CLK tAC(2)See figures 4 and 5 as applicable, Positive edge (CL = 2) 9,10,11 All 7.5 ns Address hold time tAHSee figures 4 and 5 as applicable 9,10,11 All 1.5 ns Address setup time tAS9,10,11 All 1.5 ns CLK, high-level widthtCH9,10,11 All 4 ns CLK,

44、low-level widthtCL9,10,11 All 4 ns Clock cycle time, CL = 3 17/tCK39,10,11 All 10 ns Clock cycle time, CL = 2 17/tCK29,10,11 All 10 ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A

45、 5962-10230 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 6 DSCC FORM 2234 APR 97 TABLE IA. Electrical performance characteristics Continued. Test Symbol Test conditions 1/ 2/ -40C TC +105C +3.0 V VDD +3.6 V Unless otherwise specified all voltages referenced to VSSGroup A su

46、bgroups Device type Limits Unit Min Max AC Characteristics 3/ 4/ 7/ 14/ 15/ 16/ - continued. CKE hold timetCKHSee figures 4 and 5 as applicable 9,10,11 All 2 ns CKE setup timetCKS9,10,11 All 1.5 ns CS hold timetCMH9,10,11 All 2 ns RS,CAS,WE,hold time 9,10,11 All 1.5 ns DQM hold time 9,10,11 All 2.5

47、ns CS setup timetCMS9,10,11 All 2.5 ns RS,CAS,WE,setup time 9,10,11 All 1.5 ns DQM setup time 9,10,11 All 1.5 ns Data in hold timetDH9,10,11 All 2.5 ns Data in setup timetDS9,10,11 All 1.5 ns Data out High-Z time, CL = 3tHZ39,10,11 All 9 ns Data out High-Z time, CL = 2tHZ29,10,11 All 9 ns Data out L

48、ow-Z timetLZ9,10,11 All 1 ns Data out hold time (load)tOH9,10,11 All 2.7 ns Data out hold time (no load) 18/ tOHN9,10,11 All 1.8 ns ACTIVE-to-PRECHARGE command period 18/ tRAS9,10,11 All 44 60K ns ACTIVE-to-ACTIVE command periodtRC9,10,11 All 66 ns ACTIVE-to-READ or WRITE delaytRCD9,10,11 All 20 ns Refresh period (8,192 rows) 19/ tREF9,10,11 All 32 ms AUTO REFRESH period tRFC9,10,11 All 66 ns PRECHARGE command period tRP9,10,11 All 20