DLA DSCC-VID-V62 04720 REV B-2011 MICROCIRCUIT DIGITAL ADVANCED BIPOLAR CMOS 3 3-V ABT 32-BIT BUFFER DRIVER WITH 3-STATE OUTPUTS MONOLITHIC SILICON.pdf
《DLA DSCC-VID-V62 04720 REV B-2011 MICROCIRCUIT DIGITAL ADVANCED BIPOLAR CMOS 3 3-V ABT 32-BIT BUFFER DRIVER WITH 3-STATE OUTPUTS MONOLITHIC SILICON.pdf》由会员分享,可在线阅读,更多相关《DLA DSCC-VID-V62 04720 REV B-2011 MICROCIRCUIT DIGITAL ADVANCED BIPOLAR CMOS 3 3-V ABT 32-BIT BUFFER DRIVER WITH 3-STATE OUTPUTS MONOLITHIC SILICON.pdf(12页珍藏版)》请在麦多课文档分享上搜索。
1、 REVISIONSLTR DESCRIPTION DATE APPROVEDA Correct lead finish. - CFS 05-12-02 Thomas M. Hess B Update boilerplate paragraphs to current requirements. - PHN 11-07-22 Thomas M. Hess CURRENT DESIGN ACTIVITY CAGE CODE 16236 HAS CHANGED NAMES TO: DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 Prepared in
2、 accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV B B B B B B B B B B B B PAGE 1 2 3 4 5 6 7 8 9 10 11 12 PMIC N/A PREPARED BY Charles F. Saffle DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO 43218-3990 Original date of drawing CHECKED BY Charles F. Saffle TI
3、TLE MICROCIRCUIT, DIGITAL, ADVANCED BIPOLAR CMOS, 3.3-V ABT 32-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS, MONOLITHIC SILICON YY-MM-DD 04-06-09 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/04720 REV B PAGE 1 OF 12 AMSC N/A 5962-V063-11 Provided by IHSNot for ResaleNo reproduction
4、or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04720 REV B PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance 3.3-V ABT 32-bit buffer/driver with 3-state outputs
5、 microcircuit, with an operating temperature range of -40C to +85C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentati
6、on: V62/04720 - 01 X A Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 SN74LVTH32244-EP 3.3-V ABT 32-bit buffer/driver with 3-state outputs 1.2.2 Case outlines. The case outlines are as specified he
7、rein. Outline letter Number of pins JEDEC PUB 95 Package style X 96 JEDEC MO-205 Plastic ball grid array 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plateC Gold pla
8、teD PalladiumE Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04720 REV B PAGE 3 1.3 Absolute maximum ratings. 1/ Supply voltage rang
9、e (VCC) . -0.5 V to +4.6 V Input voltage range (VI) . -0.5 V to 7 V 2/ Voltage range applied to any output in the high-impedance or power-off state (VO) . -0.5 V to 7 V 2/ Voltage range applied to any output in the high state (VO) -0.5 V to VCC+ 0.5 V 2/ Current into any output in the low state (IO)
10、 . 128 mA Current into any output in the high state (IO) . 64 mA 3/ Input clamp current (IIK) (VIVCC. 4/ The package thermal impedance is calculated in accordance with JESD 51-7. 5/ Long-term high-temperature storage and/or extended use at maximum recommended operating conditions may result in a red
11、uction of overall device life. See figure 1 for additional information on thermal derating. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04720 REV B PAGE 4 1.4
12、Recommended operating conditions. 1/ Supply voltage range (VCC) . 2.7 V to 3.6 V Minimum high level input voltage (VIH) 2 V Maximum low level input voltage (VIL) . 0.8 V Maximum input voltage (VI) . 5.5 V Output voltage range (VO) . 0.0 V to VCCMaximum high level output current (IOH) . -32 mA Maximu
13、m low level output current (IOL) . 64 mA Maximum input transition rise or fall rate (t/v) (Outputs enabled) 10 ns/V Minimum power-up ramp rate (t/VCC) 200 s/V Operating free-air temperature range (TA) -40C to +85C 2. APPLICABLE DOCUMENTS JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEDEC PUB 95
14、Registered and Standard Outlines for Semiconductor Devices JEDEC STD 51-7 High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages (Copies of these documents are available online at http:/www.jedec.org or from JEDEC Solid State Technology Association, 3103 North 10th Street,
15、Suite 240S, Arlington, VA 22201.) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. T
16、he unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design,
17、 construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 2. 3.5.2 Truth table. The truth table shall be as shown in figure 3. 3.5.3 Logic diagram. The log
18、ic diagram shall be as shown in figure 4. 3.5.4 Terminal connections. The terminal connections shall be as shown in figure 5. 3.5.5 Timing waveforms and test circuit. The timing waveforms and test circuit shall be as shown in figure 6. 1/ All unused inputs of the device must be held at VCCor GND to
19、ensure proper device operation. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04720 REV B PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol
20、Conditions VCCTemperature, TADevice type Limits Unit Min Max Input clamp voltage VIKII= -18 mA 2.7 V 25C, -40C to 85C All -1.2 V High level output voltage VOHIOH= -100 A 2.7 V to 3.6 V VCC 0.2 V IOH= -8 mA 2.7 V 2.4 IOH= -32 mA 3 V 2 Low level output voltage VOLIOL= 100 A 2.7 V 0.2 V IOL= 24 mA 0.5
21、IOL= 16 mA 3 V 0.4 IOL= 32 mA 0.5 IOL= 64 mA 0.55 Input current IIVI= 5.5 V 0 V or 3.6 V 10 A Control inputs. VI= VCCor GND 3.6 V 1 Data inputs, VI= VCC1 Data inputs, VI= 0 V -5 Input/output power-off leakage current IoffVIor VO= 0 V to 4.5 V 0 V 100 A Input current (hold) II(hold)Data inputs, VI= 0
22、.8 V 3 V 75 AData inputs, VI= 2 V -75 Data inputs. VI= 0 V to 3.6 V 2/ 3.6 V 500 Off state output current high IOZHVO= 3 V 3.6 V 5 A Off state output current low IOZLVO= 0.5 V 3.6 V -5 A3-state output current power-up IOZPUVO= 0.5 V to 3 V OE = dont care 0 V to 1.5 V 100 A 3-state output current pow
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