DLA DSCC-DWG-V62 14601-2013 MICROCIRCUIT DIGITAL-LINEAR DIGITAL DUAL SYNCHRONOUS BUCK POWER DRIVER MONOLITHIC SILICON.pdf
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1、 REVISIONS LTR DESCRIPTION DATE APPROVED Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV PAGE 1 2 3 4 5 6 7 8 9 10 11 12 PMIC N/A PREPARED BY Phu H. Nguyen DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil/ Origina
2、l date of drawing YY MM DD CHECKED BY Phu H. Nguyen TITLE MICROCIRCUIT, DIGITAL-LINEAR, DIGITAL DUAL SYNCHRONOUS BUCK POWER DRIVER, MONOLITHIC SILICON 13-11-12 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/14601 REV PAGE 1 OF 12 AMSC N/A 5962-V014-14 Provided by IHSNot for Resa
3、leNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/14601 REV PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance digital dual synchronous buck power driver mi
4、crocircuit, with an operating temperature range of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation
5、: V62/14601 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 UCD7242-EP Digital dual synchronous buck power driver 1.2.2 Case outline(s). The case outlines are as specified herein. Outline l
6、etter Number of pins Package style X 32 Plastic quad flatpack No-lead 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash pallad
7、ium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/14601 REV PAGE 3 1.3 Absolute maximum ratings. 1/ Supply voltage, (VIN) -0.3 V to 20.0 V Boot voltage, (BST): DC
8、-0.3 V to SW + 7.0 V AC 34 V 2/ Gate supply voltage, (VGG, VGG_DIS) 7 V Logic supply voltage, (BP3) 4 V Switch voltage, (SW, BSW): DC -2.0 V to VIN + 1.0 V AC 34 V 2/ Analog outputs, (TMON, IMON, Testmode) -0.3 V to 3.6 V Digital I/Os, (PWM-A, PWM-B, SRE-A, SRE-B, FLT-A, FLT-B) . -0.3 V to 5.5 V Jun
9、ction temperature, (TJ) . -55C to 150C Storage temperature range, (Tstg) . -55C to 150C ESD rating: HBM: Human Body model 2000 V CDM: Charged device model . 500 V 1.4 Thermal characteristics. Thermal metric 3/ Case outline X Units Junction to ambient thermal resistance, JA4/ 40.7 C/W Junction to cas
10、e (top) thermal resistance, JCtop5/ 17.8 Junction to board thermal resistance, JB6/ 12 Junction to top characterization parameter, JT7/ 0.1 Junction to board characterization parameter, JB8/ 11.9 Junction to case (bottom) thermal resistance, JCbot9/ 0.3 1/ Stresses beyond those listed under “absolut
11、e maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute maximum rated conditions for extend
12、ed periods may affect device reliability. 2/ AC levels are limited to within 5 ns. 3/ For more information about traditional and new thermal metrics, see manufacturer data. 4/ The junction to ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K-
13、board, as specified in JESD51-7, in an environment described in JESD51-2a. 5/ The junction to case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specified JEDEC- standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
14、 6/ The junction to board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. 7/ The junction to top characterization parameter, JT, estimates the junction temperature of a device in a real system and
15、 is extracted from the simulation data for obtaining JA, using a procedure described in JESD51-2a (sections 6 and 7). 8/ The junction to board characterization parameter, JB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining JA, u
16、sing a procedure described in JESD51-2a (sections 6 and 7). 9/ The junction to case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specified JEDEC- standard test exists, but a close description can be found in the ANSI SEMI standard G30-88 Prov
17、ided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/14601 REV PAGE 4 1.5 Recommended operating conditions. Power input voltage, VIN(internally generated VGG) . 4.75 V to 18.0 V Powe
18、r input voltage, VIN(externally generated VGG) 2.20 V to 18.0 V Externally supplied gate drive voltage, VGG. 4.75 V minimum Operating junction temperature range, TJ. -55C to 125C Switching frequency, fS. 300 kHz to 2000 kHz 2. APPLICABLE DOCUMENTS JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JES
19、D51 Methodology for the Thermal Measurement of Component Packages (Single Semiconductor Device). JESD51-2a Integrated Circuits Thermal Test Method Environment Conditions Natural Convection (Still Air) JESD51-7 High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages JESD51-8
20、Integrated Circuits Thermal Test Method Environment Conditions Junction-to-board (Copies of these documents are available online at http:/www.jedec.org or from JEDEC Solid State Technology Association, 3103 North 10th Street, Suite 240S, Arlington, VA 22201-2107). AMERICAN NATIONAL STANDARDS INSTITU
21、TE (ANSI) STANDARD ANSI SEMI STANDARD G30-88 null Test Method for Junction-to-Case Thermal Resistance Measurements for Ceramic Packages (Applications for copies should be addressed to the American National Standards Institute, Semiconductor Equipment and Materials International, 1819 L Street, NW, 6
22、 th floor, Washington, DC 20036 or online at http:/www.ansi.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (
23、optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4,
24、and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be a
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