DLA SMD-5962-10205 REV C-2013 MICROCIRCUIT MEMORY DIGITAL CMOS 1MEG X 39-BIT (40M) RADIATION-HARDENED DUAL VOLTAGE SRAM MULTICHIP MODULE.pdf

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1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Vendor requested correction to Table IA; parameter (Write disable time - tWHWL ) from 1 ns to 2 ns minimum. Remove reference to device 02 in footnote 5/ on page 3. ksr 10-07-07 Charles F. Saffle B Vendor requested corrections to Table IA; footnot

2、e additions and deletions for IDD1, IDD2, tEFR, tR and moved VDR Limit from Max to Min column. Added lid and lead details and corrected notes for Figure 1. Table 1, changed footnote 6/. Removed note from Figure 4 and moved data retention waveform from Figure 4 to Figure 5. Updated boilerplate. glg 1

3、1-10-19 Charles F. Saffle C Added lid and lead details and corrected notes for Figure 1. Corrections to paragraph 1.5 and associated footnotes. Added Table IB, SEP test limits. Corrections to Figure 2, Terminal connections. Removed device class M references. Updated boilerplate. glg 13-09-19 Charles

4、 F. Saffle REV SHEET REV C C C C C C C SHEET 15 16 17 18 19 20 21 REV STATUS REV C C C C C C C C C C C C C C OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Kenneth Rice DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil STANDARD MICROCIRCUIT DRAW

5、ING CHECKED BY Rajesh Pithadia THIS DRAWING IS AVAILABLE FOR USE BY All DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE APPROVED BY Charles F. Saffle MICROCIRCUIT, MEMORY, DIGITAL, CMOS, 1MEG X 39-BIT (40M), RADIATION-HARDENED, DUAL VOLTAGE SRAM, MULTICHIP MODULE DRAWING APPROVAL DATE 10-04-08

6、 AMSC N/A REVISION LEVEL C SIZE A CAGE CODE 67268 5962-10205 SHEET 1 OF 21 DSCC FORM 2233 APR 97 5962-E574-13 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-10205 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3

7、990 REVISION LEVEL C SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device class Q) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the

8、Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. 1.2 PIN. The PIN shall be as shown in the following example: 5962 R 10205 01 Q X A Federal RHA Device Device Case Lead stock class designator type class outline finish de

9、signator (see 1.2.1) (see 1.2.2) designator (see 1.2.4) (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices shall meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA devi

10、ce. 1.2.2 Device types. The device types shall identify the circuit function as follows: Case operating Device type Generic number 1/ Circuit function Access time temp range 01 UT8R1M39 1M X 39-bit rad-hard SRAM 20 ns -55C to +105C 02 UT8R1M39 1M X 39-bit rad-hard SRAM w/additional screening 2/ 20 n

11、s -55C to +105C 1.2.3 Device class designator. The device class designator shall be a single letter identifying the product assurance level as follows: Device class Device requirements documentation Q, V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) shal

12、l be as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style X See figure 1 132 dual cavity quad flat pack 1.2.5 Lead finish. The lead finish shall be as specified in MIL-PRF-38535 for classes Q and V. 1/ Generic numbers are also listed on the Stan

13、dard Microcircuit Drawing Source Approval Bulletin at the end of this document and will also be listed in QML-38535 and MIL-HDBK-103. 2/ Device type 02 provides QML Q product with additional testing as specified in paragraph 4.2.2d. Provided by IHSNot for ResaleNo reproduction or networking permitte

14、d without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-10205 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 3/ 4/ Supply voltage range, (VDD1) . -0.3 V dc to +2.1 V dc Supply voltage range, (VDD2) . -0.3

15、V dc to +3.8 V dc Voltage range on any pin . -0.3 V dc to +3.8 V dc Input current, dc . + 10 mA Power dissipation PD TC = 105C . 3.3 W Case temperature range, (TC) . -55C to +105C Storage temperature range, (TSTG) -65C to +150C Junction temperature, (TJ) . +150C Thermal resistance, junction-to-case,

16、 (JC): Case X 6C/W 1.4 Recommended operating conditions. 4/ Supply voltage range, (VDD1) . +1.7 V dc to +2.0 V dc Supply voltage range, (VDD2) . +2.3 V dc to +3.6 V dc Supply voltage, (VSS) . 0 V dc Input voltage, dc 0 V dc to VDD2 Case operating temperature range, (TC) -55C to +105C 1.5 Radiation f

17、eatures Maximum total dose available (effective dose rate = 1 rads(Si)/s) 10.0 x 104 rads(Si) 5/ Single event phenomenon (SEP): Effective linear energy transfer (LET) with no upsets (see 4.4.4.3) . 0.8 MeV - cm2/mg 6/ Effective LET with no latch-up (see 4.4.4.2) 100 errors or 106 ions/cm2. c. The fl

18、ux shall be between 102 and 105 ions/cm2/s. The cross-section shall be verified to be flux independent by measuring the cross-section at two flux rates which differ by at least an order of magnitude. d. The particle range shall be 20 microns in silicon. e. The test temperature shall be +25C 10C for

19、single event upset testing and at the maximum rated operating temperature +10C for single event upset testing. f. Bias conditions shall be defined by the manufacturer for latch-up measurements. g. Test four devices with zero failures. 5. PACKAGING 5.1 Packaging requirements. The requirements for pac

20、kaging shall be in accordance with MIL-PRF-38535 for device classes Q and V. 6. NOTES 6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications (original equipment), design applications, and logistics purposes. 6.1.1 Replaceability. Micr

21、ocircuits covered by this drawing will replace the same generic device covered by a contractor-prepared specification or drawing. 6.2 Configuration control of SMDs. All proposed changes to existing SMDs will be coordinated with the users of record for the individual documents. This coordination will

22、 be accomplished using DD Form 1692, Engineering Change Proposal. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-10205 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 19 DSCC FORM 2234

23、 APR 97 6.3 Record of users. Military and industrial users should inform DLA Land and Maritime when a system application requires configuration control and which SMDs are applicable to that system. DLA Land and Maritime will maintain a record of users and this list will be used for coordination and

24、distribution of changes to the drawings. Users of drawings covering microelectronic devices (FSC 5962) should contact DLA Land and Maritime-VA, telephone (614) 692-8108. 6.4 Comments. Comments on this drawing should be directed to DLA Land and Maritime-VA, Columbus, Ohio 43218-3990, or telephone (61

25、4)692-0540. 6.5 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in MIL-PRF-38535 and MIL-HDBK-1331. 6.6 Sources of supply. 6.6.1 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in MIL-H

26、DBK-103 and QML-38535. The vendors listed in QML-38535 have submitted a certificate of compliance (see 3.6 herein) to DLA Land and Maritime-VA and have agreed to this drawing. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAW

27、ING SIZE A 5962-10205 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 20 DSCC FORM 2234 APR 97 APPENDIX A Appendix A forms a part of SMD 5962- 10205 FUNCTIONAL ALGORITHMS A.1 SCOPE A.1.1 Scope. Functional algorithms are test patterns which define the exact sequence of events u

28、sed to verify proper operation of a random access memory (RAM). Each algorithm serves a specific purpose for the testing of the device. It is understood that all manufacturers do not have the same test equipment; therefore, it becomes the responsibility of each manufacturer to guarantee that the tes

29、t patterns described herein are followed as closely as possible, or equivalent patterns be used that serve the same purpose. Each manufacturer should demonstrate that this condition will be met. Algorithms shall be applied to the device in a topologically pure fashion. This appendix is a mandatory p

30、art of the specification. The information contained herein is intended for compliance. A.2 APPLICABLE DOCUMENTS. This section is not applicable to this appendix. A.3 ALGORITHMS A.3.1 Algorithm A (pattern 1). A.3.1.1 Checkerboard, checkerboard-bar. Step 1. Load memory with a checkerboard data pattern

31、 by incrementing from location 0 to maximum. Step 2. Read memory, verifying the output checkerboard pattern by incrementing from location 0 to maximum. Step 3. Load memory with a checkerboard-bar pattern by incrementing from location 0 to maximum. Step 4. Read memory, verifying the output checkerboa

32、rd-bar pattern by incrementing from location 0 to maximum. A.3.2 Algorithm B (pattern 2). A.3.2.1 March. Step 1. Load memory with background data, incrementing from minimum to maximum address locations (all “0s“). Step 2. Read data in location 0. Step 3. Write complement data to location 0. Step 4.

33、Read complement data in location 0. Step 5. Repeat steps 2 through 4 incrementing X-fast sequentially for each location in the array. Step 6. Read complement data in maximum address location. Step 7. Write data to maximum address location. Step 8. Read data in maximum address location. Step 9. Repea

34、t steps 6 through 8 decrementing X-fast sequentially for each location in the array. Step 10. Read data in location 0. Step 11. Write complement data to location 0. Step 12. Read complement data in location 0. Step 13. Repeat steps 10 through 12 decrementing X-fast sequentially for each location in

35、the array. Step 14. Read complement data in maximum address location. Step 15. Write data to maximum address location. Step 16. Read data in maximum address location. Step 17. Repeat steps 14 through 16 incrementing X-fast sequentially for each location in the array. Step 18. Read background data fr

36、om memory, decrementing X-fast from maximum to minimum address locations. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-10205 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 21 DSCC F

37、ORM 2234 APR 97 APPENDIX A Continued. Appendix A forms a part of SMD 5962- 10205 A.3.3 Algorithm C (pattern 3). A.3.3.1 XY March. Step 1. Load memory with background data, incrementing from minimum to maximum address locations (all “0s“). Step 2. Read data in location 0. Step 3. Write complement dat

38、a to location 0. Step 4. Read complement data in location 0. Step 5. Repeat steps 2 through 4 incrementing Y-fast sequentially for each location in the array. Step 6. Read complement data in maximum address location. Step 7. Write data to maximum address location. Step 8. Read data in maximum addres

39、s location. Step 9. Repeat steps 6 through 8 decrementing X-fast sequentially for each location in the array. Step 10. Read data in location 0. Step 11. Write complement data to location 0. Step 12. Read complement data in location 0. Step 13. Repeat steps 10 through 12 decrementing Y-fast sequentia

40、lly for each location in the array. Step 14. Read complement data in maximum address location. Step 15. Write data to maximum address location. Step 16. Read data in maximum address location. Step 17. Repeat steps 14 through 16 incrementing X-fast sequentially for each location in the array. Step 18

41、. Read background data from memory, decrementing Y-fast from maximum to minimum address locations. A.3.4 Algorithm D (pattern 4). A.3.4.1 CEDES - CE deselect checkerboard, checkerboard-bar. Step 1. Load memory with a checkerboard data pattern by incrementing from location 0 to maximum. Step 2. Desel

42、ect device, attempt to load memory with checkerboard-bar data pattern by incrementing from location 0 to maximum. Step 3. Read memory, verifying the output checkerboard pattern by incrementing from location 0 to maximum. Step 4. Load memory with a checkerboard-bar pattern by incrementing from locati

43、on 0 to maximum. Step 5. Deselect device, attempt to load memory with checkerboard data pattern by incrementing from location 0 to maximum. Step 6. Read memory, verifying the output checkerboard-bar pattern by incrementing from location 0 to maximum. Provided by IHSNot for ResaleNo reproduction or n

44、etworking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING BULLETIN DATE: 13-09-19 Approved sources of supply for SMD 5962-10205 are listed below for immediate acquisition information only and shall be added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and

45、 QML-38535 will be revised to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a certificate of compliance has been submitted to and accepted by DLA Land and Maritime-VA. This information bulletin is superseded by the next dated revision of MIL-HD

46、BK-103 and QML-38535. DLA Land and Maritime maintains an online database of all current sources of supply at http:/www.landandmaritime.dla.mil/Programs/Smcr/. Standard microcircuit drawing PIN 1/ Vendor CAGE number Vendor similar PIN 2/ 5962R1020501QXC 65342 UT8R1M39-21XFC 5962R1020501VXC 65342 UT8R

47、1M39-21XFC 5962R1020502QXC 65342 UT8R1M39-21XFC 1/ The lead finish shown for each PIN representing a hermetic package is the most readily available from the manufacturer listed for that part. If the desired lead finish is not listed, contact the Vendor to determine its availability. 2/ Caution. Do n

48、ot use this number for item acquisition. Items acquired to this number may not satisfy the performance requirements of this drawing. Vendor CAGE Vendor name number and address 65342 Aeroflex Colorado Springs, Inc. 4350 Centennial Blvd. Colorado Springs, CO 80907-7370 The information contained herein is disseminated for convenience only and the Government assumes no liability whatsoever for any inaccuracies in the information bulletin. Pr