BS PD IEC TS 62878-2-3-2015 Device embedded substrate Guidelines Design guide《装置内埋基板 指南 设计指南》.pdf

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1、BSI Standards Publication Device embedded substrate Part 2-3: Guidelines Design guide PD IEC/TS 62878-2-3:2015National foreword This Published Document is the UK implementation of IEC/TS 62878-2-3:2015. The UK participation in its preparation was entrusted to Technical Committee EPL/501, Electronic

2、Assembly Technology. A list of organizations represented on this committee can be obtained on request to its secretary. This publication does not purport to include all the necessary provisions of a contract. Users are responsible for its correct application. The British Standards Institution 2015.

3、Published by BSI Standards Limited 2015 ISBN 978 0 580 82124 0 ICS 31.180; 31.190 Compliance with a British Standard cannot confer immunity from legal obligations. This Published Document was published under the authority of the Standards Policy and Strategy Committee on 30 April 2015. Amendments/co

4、rrigenda issued since publication Date Text affected PUBLISHED DOCUMENT PD IEC/TS 62878-2-3:2015 IEC TS 62878-2-3 Edition 1.0 2015-03 TECHNICAL SPECIFICATION SPECIFICATION TECHNIQUE Device embedded substrate Part 2-3: Guidelines Design guide Substrat avec appareil(s) intgr(s) Partie 2-3: Directives

5、Guide de conception INTERNATIONAL ELECTROTECHNICAL COMMISSION COMMISSION ELECTROTECHNIQUE INTERNATIONALE ICS 31.180; 31.190 ISBN 978-2-8322-2403-8 Registered trademark of the International Electrotechnical Commission Marque dpose de la Commission Electrotechnique Internationale Warning! Make sure th

6、at you obtained this publication from an authorized distributor. Attention! Veuillez vous assurer que vous avez obtenu cette publication via un distributeur agr. colour inside PD IEC/TS 62878-2-3:2015 2 IEC TS 62878-2-3:2015 IEC 2015 CONTENTS FOREWORD . 4 INTRODUCTION . 6 1 Scope 7 2 Normative refer

7、ences. 7 3 Terms, definition and abbreviations 7 3.1 Terms and definitions 7 3.2 Abbreviations 7 4 Structure of device embedded substrates . 8 4.1 General . 8 4.2 Specification of the top and bottom surfaces of a device embedded substrate 8 4.3 Definition of layers of a device embedded substrate . 9

8、 4.4 Conductor spacing at a terminal 12 5 Conditions to prepare base and embedding devices . 15 5.1 Conditions for base . 15 5.2 Conditions for embedding devices . 16 6 Recommendation for embedding devices . 18 7 Design specification of device embedded substrate 19 7.1 General . 19 7.2 Items to be i

9、ncluded in the design specification 19 7.2.1 Graphical indication of device embedding substrate 19 7.2.2 Design specification template . 20 Bibliography . 24 Figure 1 Definition of top and bottom surfaces of a device embedded substrate 8 Figure 2 Definition of top and bottom surfaces for mounting on

10、 a mother board . 9 Figure 3 Names of layers in pad connection . 9 Figure 4 Additional information concerning the interconnection position 10 Figure 5 Names of layers in via connection I . 11 Figure 6 Names of layers in via connection II 11 Figure 7 Names of layers in via connection III . 12 Figure

11、8 Definitions of dielectric gap and layer gap in the pad connection method . 13 Figure 9 Definitions of dielectric gap and layer gap in the via connection method 13 Figure 10 Additional illustration of dielectric gap . 14 Figure 11 Additional illustration of layer gap . 14 Figure 12 Additional drawi

12、ng 19 Figure 13 Forbidden wiring area . 20 Table 1 Name of layers of device embedded board . 12 Table 2 Recommendation for device assembly to base substrate for device embedded boards . 15 Table 3 Embedding recommendation 16 PD IEC/TS 62878-2-3:2015 3 IEC TS 62878-2-3:2015 IEC 2015 Table 4 Mounting

13、methods of semiconductor devices 17 Table 5 Embedding device . 18 Table 6 Specification of device embedded substrate 1 21 Table 7 Specification of device embedded substrate 2 22 Table 8 Specification of device embedded substrate 3 23 PD IEC/TS 62878-2-3:2015 4 IEC TS 62878-2-3:2015 IEC 2015 INTERNAT

14、IONAL ELECTROTECHNICAL COMMISSION _ DEVICE EMBEDDED SUBSTRATE Part 2-3: Guidelines Design guide FOREWORD 1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising all national electrotechnical committees (IEC National Committees). The object of

15、 IEC is to promote international co-operation on all questions concerning standardization in the electrical and electronic fields. To this end and in addition to other activities, IEC publishes International Standards, Technical Specifications, Technical Reports, Publicly Available Specifications (P

16、AS) and Guides (hereafter referred to as “IEC Publication(s)”). Their preparation is entrusted to technical committees; any IEC National Committee interested in the subject dealt with may participate in this preparatory work. International, governmental and non- governmental organizations liaising w

17、ith the IEC also participate in this preparation. IEC collaborates closely with the International Organization for Standardization (ISO) in accordance with conditions determined by agreement between the two organizations. 2) The formal decisions or agreements of IEC on technical matters express, as

18、nearly as possible, an international consensus of opinion on the relevant subjects since each technical committee has representation from all interested IEC National Committees. 3) IEC Publications have the form of recommendations for international use and are accepted by IEC National Committees in

19、that sense. While all reasonable efforts are made to ensure that the technical content of IEC Publications is accurate, IEC cannot be held responsible for the way in which they are used or for any misinterpretation by any end user. 4) In order to promote international uniformity, IEC National Commit

20、tees undertake to apply IEC Publications transparently to the maximum extent possible in their national and regional publications. Any divergence between any IEC Publication and the corresponding national or regional publication shall be clearly indicated in the latter. 5) IEC itself does not provid

21、e any attestation of conformity. Independent certification bodies provide conformity assessment services and, in some areas, access to IEC marks of conformity. IEC is not responsible for any services carried out by independent certification bodies. 6) All users should ensure that they have the lates

22、t edition of this publication. 7) No liability shall attach to IEC or its directors, employees, servants or agents including individual experts and members of its technical committees and IEC National Committees for any personal injury, property damage or other damage of any nature whatsoever, wheth

23、er direct or indirect, or for costs (including legal fees) and expenses arising out of the publication, use of, or reliance upon, this IEC Publication or any other IEC Publications. 8) Attention is drawn to the Normative references cited in this publication. Use of the referenced publications is ind

24、ispensable for the correct application of this publication. 9) Attention is drawn to the possibility that some of the elements of this IEC Publication may be the subject of patent rights. IEC shall not be held responsible for identifying any or all such patent rights. The main task of IEC technical

25、committees is to prepare International Standards. In exceptional circumstances, a technical committee may propose the publication of a Technical Specification when the required support cannot be obtained for the publication of an International Standard, despite repeated efforts, or the subject is st

26、ill under technical development or where, for any other reason, there is the future but no immediate possibility of an agreement on an International Standard. Technical Specifications are subject to review within three years of publication to decide whether they can be transformed into International

27、 Standards. IEC TS 62878-2-3, which is a Technical Specification, has been prepared by IEC technical committee 91: Electronics assembly technology. PD IEC/TS 62878-2-3:2015 5 IEC TS 62878-2-3:2015 IEC 2015 The text of this Technical Specification is based on the following documents: Enquiry draft Re

28、port on voting 91/1143/DTS 91/1164A/RVC Full information on the voting for the approval of this Technical Specification can be found in the report on voting indicated in the above table. A list of all parts in the IEC 62878 series, published under the general title Device embedded substrate, can be

29、found on the IEC website. This publication has been drafted in accordance with the ISO/IEC Directives, Part 2. The committee has decided that the contents of this publication will remain unchanged until the stability date indicated on the IEC website under “http:/webstore.iec.ch“ in the data related

30、 to the specific publication. At this date, the publication will be transformed into an International standard, reconfirmed, withdrawn, replaced by a revised edition, or amended. IMPORTANT The colour inside logo on the cover page of this publication indicates that it contains colours which are consi

31、dered to be useful for the correct understanding of its contents. Users should therefore print this document using a colour printer. PD IEC/TS 62878-2-3:2015 6 IEC TS 62878-2-3:2015 IEC 2015 INTRODUCTION This part of IEC 62878 provides guidance with respect to device embedded substrate, fabricated b

32、y embedding discrete active and passive electronic devices into one or multiple inner layers of a substrate with electric connections by means of vias, conductor plating, conductive paste, and printing. Within the IEC 62878 series, IEC 62878-1-1 specifies the test methods, IEC TS 62878-2-1 gives a g

33、eneral description of the technology, IEC TS 62878-2-3, provides guidance on design, and IEC TS 62878-2-4 specifies the test element groups. The device embedded substrate may be used as a substrate to mount SMDs to form electronic circuits, as conductor and insulator layers may be formed after embed

34、ding electronic devices. The purpose of the IEC 62878 series is to achieve a common understanding with respect to structures, test methods, design and fabrication processes and the use of the device embedded substrate in industry. PD IEC/TS 62878-2-3:2015 7 IEC TS 62878-2-3:2015 IEC 2015 DEVICE EMBE

35、DDED SUBSTRATE Part 2-3: Guidelines Design guide 1 Scope This part of IEC 62878 describes the design guide of device embedded substrates. The design guide of device embedded substrate is essentially the same as that of various electronic circuit boards. This part of IEC 62878 enables a thorough unde

36、rstanding of circuit design, structure design, board design, board manufacturing, jisso (assembly processes) and tests of products. This part of IEC 62878 is applicable to device embedded substrates fabricated by use of organic base material, which include for example active or passive devices, disc

37、rete components formed in the fabrication process of electronic wiring board, and sheet formed components. The IEC 62878 series neither applies to the re-distribution layer (RDL) nor to the electronic modules defined as an M-type business model in IEC 62421. 2 Normative references The following docu

38、ments, in whole or in part, are normatively referenced in this document and are indispensable for its application. For dated references, only the edition cited applies. For undated references, the latest edition of the referenced document (including any amendments) applies. IEC 60194, Printed board

39、design, manufacture and assembly Terms and definitions 3 Terms, definition and abbreviations 3.1 Terms and definitions For the purposes of this document, the terms and definitions given in IEC 60194 apply. 3.2 Abbreviations AABUS as agreed between user and supplier BGA ball grid array IPD integrated

40、 passive device LGA land grid array LSI large scale integration MEMS micro electro mechanical systems OSP organic solderability preservative SMD surface mount device TAB tape automated bonding WLP wafer level package PD IEC/TS 62878-2-3:2015 8 IEC TS 62878-2-3:2015 IEC 2015 4 Structure of device emb

41、edded substrates 4.1 General The name of each part of a device embedded substrate is specified in Clause 4 to assist technical understanding of the structure and to avoid misinterpretation by engineers working in the relevant industry sectors. 4.2 Specification of the top and bottom surfaces of a de

42、vice embedded substrate The definition of the top and bottom surfaces of a device embedded substrate depends on the number of devices mounted on the surface of the substrate, as shown in Figure 1. The surface on which more components are mounted is the top surface. If a substrate is mounted on a pri

43、nted wiring board (hereafter referred to as mother board), the surface of the substrate connecting to the wiring board is defined as the bottom surface even if it contains more input/output terminals (pads) (see Figure 2). If the design of the top and bottom surfaces has been AABUS, this agreement t

44、akes priority, even if it differs from the definition stated in this part of IEC 62878. Figure 1 Definition of top and bottom surfaces of a device embedded substrate IEC PD IEC/TS 62878-2-3:2015 9 IEC TS 62878-2-3:2015 IEC 2015 Figure 2 Definition of top and bottom surfaces for mounting on a mother

45、board 4.3 Definition of layers of a device embedded substrate Names and symbols of layers in a device embedded board are illustrated in Figure 3. Each layer is numbered as L1, L2 to L6 (in case of 6 layers) from the top surface. The number indicates the order of the layer with respect to the top sur

46、face. Key A Embedded component C Top surface B Base D Bottom surface Figure 3 Names of layers in pad connection In the case of via connection, the position of connecting terminals of the embedded device is different from the surrounding layer number. The component symbol and connecting position(s) a

47、re defined as illustrated in Figure 4 in order to clarify the interconnecting positions of the embedded device and of its electrical terminals with respect to construction design, pattern design, board fabrication and jisso (assembly). It is recommended to use the component symbols and names as show

48、n in a circuit diagram to use 2 to 4 indications. The position of interconnection in the case of die-bonding or mounting IEC IEC L1 L2 L3 L4 L5 L6 A C D B PD IEC/TS 62878-2-3:2015 10 IEC TS 62878-2-3:2015 IEC 2015 of a device embedded device may be expressed using another name in addition to the nam

49、e of the layer in which the device is embedded. The surface of a device is upward facing. Use upward (U) when connecting terminals are in the upward facing surface, and downward (D) when the terminals are in the downward facing surface. A three digit number is used if multiple components are embedded and/or multiple connection terminals are in the same layer. The left side number indicates the interconnecting laye