BS ISO IEC 10861-1995 Information technology - Microprocessor systems - High-performance synchronous 32-bit bus MULTIBUS II《信息技术 微处理器系统 高性能同步32位总线 多总线Ⅱ》.pdf

《BS ISO IEC 10861-1995 Information technology - Microprocessor systems - High-performance synchronous 32-bit bus MULTIBUS II《信息技术 微处理器系统 高性能同步32位总线 多总线Ⅱ》.pdf》由会员分享，可在线阅读，更多相关《BS ISO IEC 10861-1995 Information technology - Microprocessor systems - High-performance synchronous 32-bit bus MULTIBUS II《信息技术 微处理器系统 高性能同步32位总线 多总线Ⅱ》.pdf（136页珍藏版）》请在麦多课文档分享上搜索。

1、BRITISH STANDARD BS ISO/IEC 10861:1994 Implementation of ISO/IEC10861:1994 Information technology Microprocessor systems High-performance synchronous32-bit bus: MULTIBUSIIBS ISO/IEC10861:1994 This British Standard, having been prepared under the directionof the Information Systems Technology Assembl

2、y,was published underthe authority of the Standards Board and comes into effect on 15July1995 BSI 01-2000 The following BSI references relate to the work on this standard: Committee reference IST/6/10 Draft for comment 90/66795DC ISBN 0 580 24377 X Committees responsible for this BritishStandard The

3、 preparation of this British Standard was entrusted by Technical CommitteeIST/6, Data Communications, to Technical Subcommittee IST/6/10, IEC/CLC Monitoring Subcommittee, upon which the following bodies were represented: British Telecommunications plc Digital Equipment Co. Ltd. Electrical Contractor

4、s Association Electricity Association Institution of Electrical Engineers Nine Tiles Computer Systems Ltd. Amendments issued since publication Amd. No. Date CommentsBS ISO/IEC10861:1994 BSI 01-2000 i Contents Page Committees responsible Inside front cover National foreword ii Foreword viii Text of I

5、SO/IEC10861 1BS ISO/IEC10861:1994 ii BSI 01-2000 National foreword This British Standard reproduces verbatim ISO/IEC 10861:1994 and implements it as the UK national standard. This British Standard is published under the direction of the Information Systems Technology Assembly whose Technical Subcomm

6、ittee IST/6/10 has the responsibility to: aid enquirers to understand the text; present to the responsible international committee any enquiries on interpretation, or proposals for change, and keep UK interests informed; monitor related international and European developments and promulgate them in

7、the UK. NOTEInternational and European Standards, as well as overseas standards, are available from Customer Services, BSI, 389 Chiswick High Road, LondonW44AL. A British Standard does not purport to include all the necessary provisions of a contract. Users of British Standards are responsible for t

8、heir correct application. Compliance with a British Standard does not of itself confer immunity from legal obligations. Summary of pages This document comprises a front cover, an inside front cover, pages i and ii, theISO/IEC title page, pages ii to x, pages 1 to 121 and a back cover. This standard

9、has been updated (see copyright date) and may have had amendments incorporated. This will be indicated in the amendment table on the inside front cover.ISO/IEC10861:1994 ii BSI 01-2000 Abstract: The operation, functions, and attributes of a parallel system bus (PSB), called MULTIBUSII, are defined.

10、A high-performance backplane bus intended for use in multiple processor systems, the PSB incorporates synchronous, 32-bit multiplexed address/data, with error detection, and uses a10MHz bus clock. This design is intended to provide reliable state-of-the-art operation and to allow the implementation

11、of cost-effective, high-performance VLSI for the bus interface. Memory,I/O, message, and geographic address spaces are defined. Error detection and retry are provided for messages. The message-passing design allows a VLSI implementation, so that virtually all modules on the bus will utilize the bus

12、at its highest performance32 to 40Mbyte/s. An overview of PSB, signal descriptions, the PSB protocol, electrical characteristics, and mechanical specifications are covered. Keywords: High-performance synchronous32-bit bus, MULTIBUS II, system bus architecturesISO/IEC10861:1994 iv BSI 01-2000 Content

13、s Page Foreword viii Introduction 1 1 General overview to the IEEE 1296 Standard 3 1.1 Scope 3 1.2 Normative references 3 2 Definitions 3 3 Guide to notation 8 3.1 General 8 3.2 Signal notation 9 3.3 Figure notation 9 3.4 Notation in state-flow diagrams 10 3.5 Notation for multiple bit data represen

14、tation 10 4 PSB overview 11 4.1 General 11 4.2 Address/data path and system control signals 11 4.3 Message-passing facility 12 4.4 Interconnect facility 12 4.5 Synchronous operation of the PSB 12 4.6 Bus operations on the PSB 12 4.7 Central services module 15 5 Signal descriptions 15 5.1 General 15

15、5.2 Signal groups 15 6 PSB protocol 22 6.1 General 22 6.2 Arbitration operation 23 6.3 Transfer operation 33 6.4 Exception operation 50 6.5 Central control functions 53 6.6 State-flow diagrams 60 7 Electrical characteristics 72 7.1 General 72 7.2 AC timing specifications 73 7.3 DC specifications for

16、 signals 78 7.4 Current limitations per connector 80 7.5 Pin assignments 80 8 Mechanical specifications 82 8.1 General 82 8.2 Board sizes and dimensions 83 8.3 Printed board layout considerations 85 8.4 Front panel 85 8.5 Connectors 85 8.6 Backplanes 86 9 IEEE 1296 System Interface specification 94

17、9.1 Overview 94 9.2 Interconnect space operation 95 9.3 I/O space operation 109 9.4 Memory space operations 109 9.5 Message space operations 110 10 IEEE 1296 capabilities 119ISO/IEC10861:1994 BSI 01-2000 v Page 10.1 Characteristic codes 119 Annex A (informative) Recommended documentation practices 1

18、20 Figure 3.3-1 Figure notation example 10 Figure 4.1-1 Block diagram of the PSB interface 11 Figure 4.6-1 Bus operation relationships 12 Figure 4.6-2 Block diagram of bus operations 13 Figure 4.6-3 Block diagram of bus operations with errors 14 Figure 5.2-1 Backplane connection of LACHn* 22 Figure

19、6.1-1 Bus operation details 23 Figure 6.2-1 Reset sequence 24 Figure 6.2-2 Timing sequence with bus locked 26 Figure 6.2-3 Timing sequence for bus release 27 Figure 6.2-4 Typical arbitration operation sequence 28 Figure 6.2-5 Arbitration ID interface example (at each requesting agent) 29 Figure 6.2-

20、6 Timing sequences for bus acquisition 31 Figure 6.2-7 Timing sequence for high priority bus acquisition 32 Figure 6.3-1 Block diagram of single read data transfer 34 Figure 6.3-2 Timing for a single read data transfer 35 Figure 6.3-3 Block diagram of single write data transfer 36 Figure 6.3-4 Timin

21、g for single write data transfer 37 Figure 6.3-5 Block diagram of sequential data transfer 37 Figure 6.3-6 Timing for sequential read data transfer 38 Figure 6.3-7 Timing for sequential write data transfer 39 Figure 6.3-8 Block diagram of broadcast message 40 Figure 6.3-9 Timing for broadcast messag

22、e 40 Figure 6.3-10 Timing sequence for LOCK operation 41 Figure 6.3-11 Timing sequence for transfer-width error 42 Figure 6.3-12 Timing sequence for continuation error 43 Figure 6.3-13 Address format for sequences using memory address space 45 Figure 6.3-14 Block diagram of sequential data transfers

23、 in memory space 45 Figure 6.3-15 Address format for sequences using I/O address space 46 Figure 6.3-16 Address format for sequences using message address space 47 Figure 6.3-17 Address format for interconnect address space 47 Figure 6.3-18 Interface requirements for data alignment 50 Figure 6.4-1 E

24、xception cycle signal relationships 51 Figure 6.4-2 Signalling a TIMOUT* exception 52 Figure 6.4-3 Signalling a BUSERR* exception 54 Figure 6.5-1 Power-on system reset sequence 56 Figure 6.5-2 Warm-start reset sequence 57 Figure 6.5-3 Power failure recovery sequence 57 Figure 6.5-4 Example arbitrati

25、on/cardslot ID assignment timing sequence 60 Figure 6.5-5 Reset sequence 61 Figure 6.6-1 State-flow diagram for monitoring transfer operations 62ISO/IEC10861:1994 vi BSI 01-2000 Page Figure 6.6-2 Slate-flow diagram for agents monitoring arbitration operations 63 Figure 6.6-3 State-flow diagram for a

26、rbitration operations 65 Figure 6.6-4 State-flow diagram for requesting agents in a transfer operation 67 Figure 6.6-5 Stale-flow diagram for replying agents 69 Figure 7.2-1 BCLK* and CCLK* timing relationships at the CSM 73 Figure 7.2-2 BCLK* and CCLK* timing relationships for receivers 74 Figure 7

27、.2-3 Driver timing parameters 75 Figure 7.2-4 Timing parameters for signal receivers 76 Figure 7.2-5 Cold-start timing parameters 77 Figure 7.2-6 Warm-start timing parameters 77 Figure 7.2-7 Power Failure and recovery timing parameters 78 Figure 8.1-1 Double eurocard connector definitions 83 Figure

28、8.1-2 Triple eurocard connector definitions 84 Figure 8.1-3 Typical subrack 84 Figure 8.2-1 Double-high board dimensions 86 Figure 8.3-1 Board layout considerations for front panels 87 Figure 8.4-1 Front panel dimensions 88 Figure 8.4-2 Board spacing and front panel relationships 89 Figure 8.5-1 Rel

29、ationship of boards and connectors 90 Figure 8.6-1 Backplane and mounting rail relationship 91 Figure 8.6-2 Backplane connector layout 92 Figure 8.6-3 Off-board termination 93 Figure 8.6-4 On-board termination 93 Figure 8.6-5 PSB backplane layer thickness 94 Figure 9.2-1 Interconnect address format

30、96 Figure 9.2-2 Interconnect space format 96 Figure 9.2-3 Structure of the compliant interconnect template 97 Figure 9.2-4 Function record chaining 98 Figure 9.2-5 Function record format 99 Figure 9.2-6 Interconnect template organization 100 Figure 9.2-7 Flowchart for reading date and time 105 Figur

31、e 9.2-8 Flowchart for writing time 106 Figure 9.2-9 Flowchart for writing date 107 Figure 9.5-1 Unsolicited message format 111 Figure 9.5-2 Solicited message format 112 Figure 9.5-3 Solicited message transfer 114 Figure 9.5-4 General interrupt message packet 116 Figure 9.5-5 Broadcast interrupt mess

32、age packet 116 Figure 9.5-6 Buffer request message packet 117 Figure 9.5-7 Buffer grant message packet 117 Figure 9.5-8 Buffer grant message packet 118 Figure 9.5-9 Data packet 118 Table 3.2-1 Signal notation 9 Table 5.2-1 Signal groups on the PSB 15 Table 5.2-2 Summary of functions of SC* signals 1

33、7 Table 5.2-3 Functions of SC* during request phase 18 Table 5.2-4 Functions of SC* during reply phase 19ISO/IEC10861:1994 BSI 01-2000 vii Page Table 6.2-1 Arbitration priority protocol 25 Table 6.2-2 Arbitration ID comparison example 30 Table 6.3-1 Agent status codes 41 Table 6.3-2 Address space su

34、mmary 44 Table 6.3-3 Data alignments for operations using memory andI/O space 48 Table 6.3-4 Data alignment for message space operations 49 Table 6.3-5 Data alignment for operations using interconnect space 49 Table 6.3-6 Width errors for memory and I/O space operations 49 Table 6.5-1 Cardslot and d

35、efault arbitration ID assignment 59 Table 7.1-1 Abbreviations used for the electrical specification 72 Table 7.2-1 Clock specification for the CSM 73 Table 7.2-2 Clock specifications for receivers 74 Table 7.2-3 Timing parameters for signal driver 75 Table 7.2-4 Timing parameters for signal receiver

36、s 76 Table 7.2-5 Cold-start control timing 76 Table 7.2-6 Warm-start control timing 77 Table 7.2-7 Power failure and recovery timing 78 Table 7.3-1 DC specifications for signal drivers 79 Table 7.3-2 DC specifications for signal receivers 79 Table 7.3-3 Backplane termination requirements 80 Table 7.

37、4-1 Power limitations for a one-connector agent 80 Table 7.4-2 Power limitations for a two-connector agent 80 Table 7.5-1 PSB connector pinout 81 Table 7.5-2 P2 connector recommended power pinout 82 Table 8.6-1 PSB backplane characteristics 89 Table 8.6-2 Cardslot numbering sequence for large backpl

38、anes 89 Table 9.2-1 Interconnect address space summary 95 Table 9.2-2 Header record format 98 Table 9.2-3 Predefined function records 101 Table 9.2-4 Format of the extended record 101 Table 9.2-5 CSM record format 102 Table 9.2-6 Reset codes for the CSM command register 102 Table 9.2-7 Format of the

39、 time/date record 103 Table 9.2-8 Time/date commands 103 Table 9.2-9 Day of week register encoding 108 Table 9.2-10 End-of-template record format 108 Table 9.2-11 Minimum compliant interconnect template format 108 Table 9.3-1 I/O address space summary 109 Table 9.4-1 Memory address space summary 109

40、 Table 9.5-1 Message address space summary 110 Table 9.5-2 Duty cycle computation 114 Table 9.5-3 Packet formats on the bus 115 Table 10.1-1 Characteristic codes 119 Table A.12-1 Recommended documentation example 121ISO/IEC10861:1994 viii BSI 01-2000 Foreword ISO (the International Organization for

41、Standardization) and IEC (the International Electrotechnical Commission) form the specialized system for worldwide standardization. National bodies that are members of ISO or IEC participate in the development of International Standards through technical committees established by the respective orga

42、nization to deal with particular fields of technical activity. ISO and IEC technical committees collaborate in fields of mutual interest. Other international organizations, governmental and nongovernmental, in liaison with ISO and IEC, also take part in the work. In the field of information technolo

43、gy, ISO and IEC have established a joint technical committee, ISO/IEC JTC1. Draft International Standards adopted by the joint technical committee are circulated to national bodies for voting. Publication as an International Standard requires approval by at least75% of the national bodies casting a

44、vote. In1990, ANSI/IEEE Std1296:1987 was adopted by ISO/IEC JTC1, as draft International Standard ISO/IEC/DIS 10861. This draft was subsequently approved by ISO/IECJTC1 in the form of this edition, which is published as International Standard ISO/IEC 10861:1994.ISO/IEC10861:1994 BSI 01-2000 ix IEEE

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