JEDEC JESD22-B106D-2008 Resistance to Solder Shock for Through-Hole Mounted Devices《通孔安装装置用焊料冲击阻力》.pdf

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1、JEDEC STANDARD Resistance to Solder Shock for Through-Hole Mounted Devices JESD22-B106D (Revision of JESD22-B106C, February 2005) APRIL 2008 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JE

2、DEC Board of Directors level and subsequently reviewed and approved by the JEDEC legal counsel. JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of pr

3、oducts, and assisting the purchaser in selecting and obtaining with minimum delay the proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally. JEDEC standards and publications are adopted without regard to whether or not the

4、ir adoption may involve patents or articles, materials, or processes. By such action JEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC standards or publications. The information included in JEDEC standards and publicatio

5、ns represents a sound approach to product specification and application, principally from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard or publication may be further processed and ultimately become an ANSI standard. No clai

6、ms to be in conformance with this standard may be made unless all requirements stated in the standard are met. Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication should be addressed to JEDEC at the address below, or call (703) 907-7559 or www.jedec.org

7、 Published by JEDEC Solid State Technology Association 2008 2500 Wilson Boulevard Arlington, VA 22201-3834 This document may be downloaded free of charge; however JEDEC retains the copyright on this material. By downloading this file the individual agrees not to charge for or resell the resulting ma

8、terial. PRICE: Please refer to the current Catalog of JEDEC Engineering Standards and Publications online at http:/www.jedec.org/Catalog/catalog.cfm Printed in the U.S.A. All rights reserved PLEASE! DONT VIOLATE THE LAW! This document is copyrighted by JEDEC and may not be reproduced without permiss

9、ion. Organizations may obtain permission to reproduce a limited number of copies through entering into a license agreement. For information, contact: JEDEC Solid State Technology Association 2500 Wilson Boulevard Arlington, Virginia 22201-3834 or call (703) 907-7559 JEDEC Standard 22-B106D Page 1 Te

10、st Method B106D (Revision of Test Method B106C) TEST METHOD B106D RESISTANCE TO SOLDER SHOCK FOR THROUGH-HOLE MOUNTED DEVICES (From JEDEC Board Ballot JCB-98-98, JCB-05-12, and JCB-08-09, formulated under the cognizance of JC-14.1 Committee on Reliability Test Methods for Packaged Devices.) 1 Scope

11、This test method is used to determine whether solid state devices can withstand the effect of the temperature shock to which they will be subjected during soldering of their leads in a solderwave process and/or solder fountain (rework/replacement) process. The heat is conducted through the leads int

12、o the device package from solder heat at the reverse side of the board. This test method shall not be used to simulate wave soldering of surface mount device packages that are glued onto the same side of the board as the solder wave and are fully submerged into the solder wave. The test method for s

13、imulating SMT devices through the wave is JESD22-A111, “Evaluation Procedure for Determining Capability to Bottom Side Board Attach by Full Body Solder Immersion of Small Surface Mount Solid State Devices“. In order to establish a standard test procedure for the most reproducible methods, the solder

14、 dip method is used because of its more controllable conditions. This procedure will determine whether devices are capable of withstanding the soldering temperature encountered in printed wiring board assembly operations, without degrading their electrical characteristics or internal connections. Th

15、is test is destructive and may be used for qualification, lot acceptance and as a product monitor. 2 Apparatus 2.1 Solder Pot A solder pot of sufficient size to contain at least 0.91 kg (2 lbs.) of solder shall be used. Its dimensions shall allow immersion of the leads to the depth specified in 4.3

16、without touching the bottom of the pot. The apparatus shall be capable of maintaining the solder at the temperature specified in 4.2 2.2 Dipping Device A mechanical dipping device shall be used that is capable of controlling the rates of immersion and emersion of the leads and providing the dwell ti

17、me specified in 4.3. JEDEC Standard 22-B106D Page 2 Test Method B106D (Revision of Test Method B106C) 2 Apparatus (contd) 2.3 Heatsinks or shielding If a heatsink or shielding is typically applied to the device prior to the solderwave process, then such heatsinks or shielding shall be attached to th

18、e devices prior to this test and shall be specified in the applicable procurement document. 3 Materials 3.1 Solder The solder shall conform to J-STD-006, Requirements for Electronic Grade Solder Alloys and Fluxed and Non-Fluxed Solid Solders for Electronic Soldering Applications. SnPb alloy composit

19、ion: Sn60Pb40 or Sn63Pb37 (Sn 1%). Pb-free solder alloy composition: Sn95.5Ag3.9Cu0.6, allowing variation of the Ag content between 3.0 4.0 wt% and Cu content between 0.5 1.0 wt%. Other lead-free alloy compositions may be used by agreement between user and supplier. 4 Procedure 4.1 Special preparati

20、on of specimens Any special preparation of the specimens prior to testing shall be as specified in the individual specification. This preparation may include operations such as bending, or other relocation of leads, and the attachment of heat sinks or protective shielding prior to preheating and sol

21、der dipping. 4.2 Preparation of the solder bath The dross shall be skimmed from the surface of the molten solder just prior to dipping the part. 4.2.1 SnPb solder bath temperature The SnPb solder bath shall be maintained at a temperature of 260 C 5 C. 4.2.2 Pb-free solder bath temperature The Pb-fre

22、e solder bath shall be maintained at a temperature of 270 C 5 C. JEDEC Standard 22-B106D Page 3 Test Method B106D (Revision of Test Method B106C) 4 Procedure (contd) 4.3 Solder dip The part shall be attached to the dipping device (see 2.2) and the leads immersed in the molten solder to within 1 mm (

23、0.04“) of the body of the device under test. The immersion and emersion rates shall be 25 6 mm (1 “) per second. See sections 4.3.1 and 4.3.2 for the appropriate dwell time in the solder. After the dipping process, the part shall be allowed to cool in air. 4.3.1 SnPb solder bath dip dwell time The d

24、well time for a SnPb solder bath shall be 10 +2/-0 seconds. 4.3.2 Pb-free solder bath dip dwell time 4.3.2.1 Pb-free solder bath dip dwell time The dwell time for a Pb-free solder bath shall be 7 +2/-0 seconds. 4.3.2.2 Optional Pb-free solder bath dip dwell time for solder fountain rework If the par

25、t must survive a solder fountain rework process, the dwell time for a Pb-free solder bath shall be 15 +2/-0 seconds. 4.4 Precautions Prior to and after the solder immersion, precautionary measures shall be taken to prevent undue exposure of the part to the heat from the solder bath. In addition, car

26、e must be taken to prevent thermal shocking the part when placed into flux removal agent. 4.5 Measurements Hermeticity tests for hermetic devices, visual examination, and electrical measurements, that consist of parametric and functional tests shall be made as specified in the applicable procurement

27、 document. 4.6 Failure criteria A device shall be defined as a failure if hermeticity for hermetic devices cannot be demonstrated, if parametric limits are exceeded, or if functionality cannot be demonstrated under nominal and worst case conditions specified in the applicable procurement document. M

28、echanical damage such as cracking, chipping, or breaking of the package, (10 - 20X magnification), will also be considered a failure provided such damage was not induced by fixturing or handling. JEDEC Standard 22-B106D Page 4 Test Method B106D (Revision of Test Method B106C) 5 Summary The following

29、 details shall be specified in the applicable procurement document: a) The use of heatsinks or shielding, if applicable (see 2.3). b) Special preparation of specimens, if applicable (see 4.1). c) Temperature of solder bath, if other than as specified in 4.2. d) Time and depth of immersion, if other

30、than as specified in 4.3, and if 4.3.2.2 is required. e) Failure criteria per 4.6 or other used. f) Sample size and quality level. JEDEC Standard 22-B106D Page 5 Test Method B106D (Revision of Test Method B106C) Annex A (informative) Process information collected to generate this revision For this r

31、evision of B106, the process data stated below were collected. These data state that solder wave pot temperatures can be 10C higher for Pb-free solder than for eutectic SnPb solder, especially for relatively thick, complex boards. However, data were not yet available for the largest and most complex

32、 boards. Pb-Free Wave Company solder pot tempera-ture dwell time board thickness preheat temperature, board and/or component temp. preheat duration Other comments 265 +/-5C 3 to 4 seconds 2.0 mm (79 mils),6 layer 120C comp. lead 0.7 m/min conveyorA 265 +/-5C 5 seconds 2.2 mm (87 mils),14 layer 110C

33、comp. lead 0.6 m/min conveyorB 265 +/-5C 2-3 seconds 1.6 to 2.0mm (63 to 79 mils) 140C, board max. 1 m/min conveyor, 265 +/-5C 3 to 6.5 seconds thick (90 mils) 140C, comp. body C 260 +/-5C 2 to 4 seconds thin (62 mils) 125C, comp body single wave D 265-270C 2-5 sec., single wave 62 mils 110-140C com

34、p. body 2 minutes E 260-265C 3-8 sec 63 to 135 mils 110-130C PWB topside 2-3 minutes Pb-Free Rework (solder fountain) Company solder pot tempera-ture dwell time / contact with solder pot # of solder pot contacts for replacement of component board thicknesspreheat temperature, board and/or component

35、temp. preheat duration A 265 +/-5C 5-10 seconds, (8-10 sec. typical) 2 typical, but could be 3 62 mils 150C board and comp. body 15 minutes in oven C 277 +/- 5C Depends on component type and board thickness; up to 25 sec for 62 mils, 45 sec for 93 mils & up Most (85%) of DT boards rework is due to l

36、ead not through (or tilt) so component is not really replaced just re-seated. 62 mils 140C for 62mil thick boards 145C for 93 mils and thicker boards 5 minutes in oven D 265 +/-5C 5-10 seconds, (8-10 sec. typical) 2 typical, but could be 3 62 mils 150C board and comp. body 15 minutes in oven E 271-2

37、77C 10-15 seconds 1 contact 62 - 135 mils 150C (board & comp.) time to ramp up to 150C The conditions stated in 4.2.2 and 4.3.2 are based on the data in the tables above. The total dwell time and the preheat conditions for Pb-free solder fountain rework are more severe than initial attach, and the w

38、orking group concluded that this test method needed to provide test conditions to cover the rework process. In gathering the data from multiple companies, the working group asked each company what criteria were used in determining when solder fountain rework would be used versus hand soldering. The

39、working group found that multiple factors determined the method used. There was no direct correlation between the size of the package being reworked and the method used. For these reasons, it was determined that this revision should include optional conditions for parts that need to be qualified for

40、 solder fountain rework. JEDEC Standard 22-B106D Page 6 Test Method B106D (Revision of Test Method B106C) Annex B (informative) Differences between JESD22-B106D and JESD22-B106C This annex briefly describes most of the changes made to entries that appear in this standard, JESD22-B106D, compared to i

41、ts predecessor, JESD22-B106C (February 2005). If the change to a concept involves any words added or deleted (excluding deletion of accidentally repeated words), it is included. Some punctuation changes are not included. Page Description of change 1 Title change to better state that this is a therma

42、l shock test method. 1 Scope, 1stparagraph, reiterate shock, and add reference to solder fountain rework 1 Scope, 2ndparagraph, re-emphasize difference between this method and 22-A111 2 In 3.1, removed A suffix to SnPb solders and removed the NOTE. 2 In 4.2, added clauses 4.2.1 and 4.2.2 to denote d

43、ifferent temperatures for SnPb and Pb-free solders. 3 In 4.3, added clauses 4.3.1 and 4.3.2 to denote different dwell durations for SnPb and Pb-free solders and duration for Pb-free solder fountain rework. 4 In 5 d), Added reference to 4.3.2.2 5 Added new informative Annex A to provide background on

44、 information used to substantiate the Pb-free solder temperatures and dwell durations. Rev. 9/02 Standard Improvement Form JEDEC JESD22-B106D The purpose of this form is to provide the Technical Committees of JEDEC with input from the industry regarding usage of the subject standard. Individuals or

45、companies are invited to submit comments to JEDEC. All comments will be collected and dispersed to the appropriate committee(s). If you can provide input, please complete this form and return to: JEDEC Attn: Publications Department 2500 Wilson Blvd. Suite 220 Arlington, VA 22201-3834 Fax: 703.907.75

46、83 1. I recommend changes to the following: Requirement, clause number Test method number Clause number The referenced clause number has proven to be: Unclear Too Rigid In Error Other 2. Recommendations for correction: 3. Other suggestions for document improvement: Submitted by Name: Phone: Company: E-mail: Address: City/State/Zip: Date: