ETSI ETR 080-1996 Transmission and Multiplexing (TM) Integrated Services Digital Network (ISDN) Basic Rate Access Digital Transmission System on Metallic Local Lines Second Edition.pdf
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1、ETSI ETR*OBO b 3400855 0347573 54b -7 1 ECHNICAL ETR 080 November 1996 Second Edition Source: ETSI TC-TM Reference: RTR/TM-06004 ICs: 33.080 Key words: ISDN, transmission, basic, rate, access, local loop, coding Transmission and Multiplexing (TM); Integrated Services Digital Network (ISDN) basic rat
2、e access; Digital transmission system on metallic local lines ETSI European Telecommunications Standards Institute ETSI Secretariat Postai address: F-O6921 Sophia Antipolis CEDEX - FRANCE Office address: 650 Route des Lucioles - Sophia Antipolis - Valbonne - FRANCE X.400: c=fr, a=atlas, p=etsi, s=se
3、cretarat - Internet: secretariat Qetsi.fr Tel.: +33 4 92 94 42 O0 - Fax: +33 4 93 65 47 16 Copyright Notification: No part may be reproduced except as authorized by written permission. The copyright and the foregoing restriction extend to reproduction in all media. O European Telecornmunications Sta
4、ndards Institute 1996. All rights reserved. Page 2 ETSI ETR*OBO 96 3400855 0347572 482 ETR 080: November 1996 Whilst every care has been taken in the preparation and publication of this document, errors in content, typographical or otherwise, may occur. If you have comments concerning its accuracy,
5、please write to “ETSI Editing and Committee Support Dept.“ at the address shown on the title page. ETSI ETR*OBO 96 m 3400855 0347573 319 m Page 3 ETR 080: November 1996 Contents Foreword . 9 1 2 3 4 5 6 7 8 Scope 11 1.1 Objectives 12 References 12 Abbreviations . 13 Functions . 14 4.1 B-channel . 14
6、 4.2 Dchannel . 14 4.3 Bit timing 14 4.5 Frame alignment 14 Activation from LT or NT1 15 4.7 Deactivation . 15 4.8 Power feeding 15 4.4 Octet timing 14 4.6 4.9 Operations and maintenance . 15 Transmission medium . 16 5.2 Minimum ISDN requirements . 16 5.3 5.4 DLL characteristics 17 5.4.1 Principal c
7、haracteristics . 17 5.4.2 Crosstalk . 17 5.4.3 5.4.4 Impulse noise 18 5.4.5 Micro interruptions . 18 5.1 Description . 16 DLL physical characteristics 16 Unbalance about earth 18 System performance . 18 6.1 Performance requirements 18 System performance with Regenerators (REGS) 19 6.2 Performance me
8、asurements . 19 DLL physical models . 19 6.2.2 Intrasystem crosstalk 22 Impulse noise modelling 22 6.2.3.1 Types of impulsive noise . 22 6.2.3.2 Measurement arrangement . 23 Performance tests . 24 6.2.4.1 TEST 1 24 Micro interruption test 25 Longitudinal conversion loss . 25 6.1.1 6.2.1 6.2.3 6.2.4.
9、2 TEST 2 24 6.2.4.3 TEST 3 25 6.2.5 Unbalance about earth . 25 6.3.1 6.3.2 Longitudinal output voltage 26 6.3 6.2.4 Transmission method 27 Activation/deactivation . 28 8.1 General 28 8.2 Physical representation of signals . 28 9 Operation and maintenance 28 ETSI ETR*O80 96 3400855 OLY7574 255 Page 4
10、 ETR 080: November 1996 9.1 9.2 CL channel 28 CL channel definition 28 CL channel requirements 28 Operation and maintenance functions 28 9.2.1 9.2.2 9.3 Metallic loop testing . 29 10 Power feeding . 29 10.1 10.2 10.3 10.4 10.5 10.6 10.7 10.8 . General 29 Power feeding functions 29 10.2.1 Power feedi
11、ng of the REG 29 10.2.2 10.2.3 Power feeding of the user network interface 29 DLL resistance 29 LT aspects . 30 10.5.1 Feeding voltage from the LT . 30 10.5.2 Dynamic power feeding requirements 30 10.5.3 LT requirements for the reset of NT1 and REG . 31 Power requirements of NT1 and regenerator 31 1
12、0.6.1 10.6.1.1 Static requirements . 31 Power requirement of regenerator 33 10.6.2.1 Static requirements . 33 10.6.2.2 Dynamic requirements 33 10.6.3 Feeding voltage to the NT1 34 10.6.4 Voltage drop across the REG . 34 10.6.5 Reset of NT1 and REG . 34 Current transient limitation 34 DC and low freq
13、uency AC termination of NT1 and REG 34 Power feeding of the NTl . 29 Wetting current 29 Power requirements of NT1 31 10.6.1.2 Dynamic requirements 31 10.6.2 11 Environmental conditions 35 1 1.1 Climatic conditions 35 11.2 Safety 35 11.4 EMC 35 Definition of a system using 2B1Q line code 36 11.3 Over
14、voltage protection 35 Annex A: A . 1 A.2 A.3 A.4 A.5 A.6 A.7 A.O Line code 36 Line baud rate . 36 A.2.1 NT1 clock tolerance 36 A.2.2 LT clock tolerance . 36 A.2.3 REG clock tolerance . 36 Frame structure 36 A.3.1 Frame length . 36 A.3.2 Bit allocation in direction LT to NT1 . 36 A.3.3 Bit allocation
15、 in direction NT1 to LT . 37 Frame word . 38 A.4.1 Frame word in direction LT to NT1 . 38 Frame alignment procedure . 38 Multiframe . 38 A.6.1 Multiframe word in direction NT1 to LT . 39 A.6.2 Multiframe word in direction LT to NT1 . 39 Frame offset between LT to NT1 and NT1 to LT frames . 39 CL cha
16、nnel 39 A.8.1 A.8.2 A.8.3 ETSI ETR*OBO 96 3400855 0347575 193 Page 5 ETR 080: November 1996 Bit rate 39 Structure 39 Protocol and procedures 39 A.8.3.1 Error monitoring function . 41 A.8.3.1.1 Cyclic redundancy check . 41 A.8.3.1.2 CRC algorithms . 41 A.8.3.1.3 Bits covered by the CRC . 43 Other CL
17、channel functions . 43 A.8.3.2.1 Far end block error bit, mandatory 43 A.8.3.2.2 The ACT bit, mandatory 43 A.8.3.2.3 The DEA bit, mandatory 43 A.8.3.2.4 NTI power status bits 43 A.8.3.2.5 NT1 Test Mode (NTM) indicator bit . 43 .a.3.2.6 Cold-Start-Only (CSO) bit 43 .a.3.2.7 DLL-Only-Activation (UOA)
18、bit . 43 .a.3.2.8 S/T- I nte rface- Activity - I nd icator (SAI) bit 44 A.8.3.2.9 Alarm Indicator Bit (AIB) 44 A.8.3.2.10 Network Indicator Bit (NIB) for network use 44 A.8.3.2.11 Reserved bits . 44 Embedded Operations Channel (EOC) functions . 44 A.8.3.3.1 EOC frame . 44 A.8.3.3.2 Mode of operation
19、 44 A.8.3.3.3 Addressing . 45 A.8.3.3.4 Definition of required EOC functions . 45 A.8.3.3.5 Codes for required EOC functions . 46 A.8.3.2 A.8.3.3 A.9 Scrambling 47 A.l O Start-uP and control . 49 A.10.1 A.10.2 A.10.3 A.10.4 A.10.5 A.10.6 Signals used for start-up and control . 50 Signals during star
20、t-up 50 A.10.1.3 Start-up sequence . 51 A.10.1.5.1 Start-up 52 A.10.1.5.2 Deactivation . 52 Timers 52 A.10.1.1 A.10.1.2 Line rate during start-up 51 A.10.1.4 Wake-up 51 A.10.1.5 Progress indicators 52 Description of the start-up procedure 53 A.10.3.1 Start-up from customer equipment . 53 A.10.3.2 St
21、art-up from the network 53 A.10.3.3 Sequence charts . 53 A.10.3.4 Transparency 56 State transition table for the LT 57 Activation times 65 State transition table for the NT1 . 57 A.11 Jitter . 65 A.11.1 A.11.2 A.11.3 A.11.4 A.11.5 A.11.6 NT1 input signal jitter tolerance . 66 NT1 output jitter limit
22、ations 66 LT input signal jitter tolerance 67 LT output jitter and synchronization . 67 REG jitter tolerance and output jitter limitations . 67 Test conditions for jitter measurements . 67 A.12 Transmitter output characteristics of NT1. REG and LT . 67 A.12.1 Pulse amplitude . 67 A.12.3 Signal power
23、 68 A.12.5 Transmitter linearity . 69 A.12.5.1 Requirements 69 Linearity test method . 69 A.12.2 Pulse shape . 67 A.12.4 Power spectral density . 69 A.12.5.2 ETSI ETR*O8O 96 3400855 OL4757b 028 Page 6 ETR 080: November 1996 A.13 Transmittedreceiver termination . 71 A.13.1 Impedance 71 Return loss 1
24、. 71 Unbalance about earth 72 Longitudinal conversion loss . 72 Appendix I (to Annex A): Extension functions of the system using 2B1Q line code . 73 A.13.2 A.13.3 A.13.3.1 1-1 Introduction . 73 1-2 NT1 Power status bits . 73 1-3 NTM bit . 74 1-4 CSO bit . 74 1-5 UOA bit . 74 1-6 SAI bit . 74 1-7 AIB
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