DLA SMD-5962-93179 REV B-2002 MICROCIRCUIT LINEAR A D CONVERTER 12-BIT CMOS MONOLITHIC SILICON《硅单片 12位交流 直流转变器 氧化物半导体线性微型电路》.pdf

《DLA SMD-5962-93179 REV B-2002 MICROCIRCUIT LINEAR A D CONVERTER 12-BIT CMOS MONOLITHIC SILICON《硅单片 12位交流 直流转变器 氧化物半导体线性微型电路》.pdf》由会员分享，可在线阅读，更多相关《DLA SMD-5962-93179 REV B-2002 MICROCIRCUIT LINEAR A D CONVERTER 12-BIT CMOS MONOLITHIC SILICON《硅单片 12位交流 直流转变器 氧化物半导体线性微型电路》.pdf（16页珍藏版）》请在麦多课文档分享上搜索。

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Changes in accordance with NOR 5962-R195-94. 94-06-01 M. A. FRYE B Update drawing to reflect current requirements. -rrp 02-04-11 R. MONNIN REV SHET REV B SHET 15 REV STATUS REV B B B B B B B B B B B B B B OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 1

2、2 13 14 PMIC N/A PREPARED BY Dan Wonnell DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY Sandra Rooney COLUMBUS, OHIO 43216 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Michael A. Frye MICROCIRCUIT, LINEAR, A/D CONVERTER, 12-BIT, CMO

3、S, MONOLITHIC SILICON AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 94-02-17 AMSC N/A REVISION LEVEL B SIZE A CAGE CODE 67268 5962-93179 SHEET 1 OF 15 DSCC FORM 2233 APR 97 5962-E336-02 DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited.Provided by IHS

4、Not for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-93179 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL B SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance

5、class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are

6、reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 - 93179 01 Q L X Federal stock class designator RHA designator (see 1.2.1) Devicetype (see 1.2.2) Device class designator Caseoutline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designa

7、tor. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indi

8、cates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 AD7876TQ 12-bit A/D converter with track/hold 1.2.3 Device class designator. The device class designator is a single letter identifying the produc

9、t assurance level as follows: Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case

10、outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style L GDIP3-T24 or CDIP4-T24 24 Dual-in-line 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, ap

11、pendix A for device class M. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-93179 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL B SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum

12、ratings. 1/ VDDto AGND . -0.3 V dc to +7.0 V dc VSSto AGND . +0.3 V dc to 7.0 V dc AGND to DGND -0.3 V dc to VDD+ 0.3 V dc VINto AGND -15 V dc to +15 V dc REFOUTto AGND . 0 V dc to VDDDigital inputs to DGND -0.3 V dc to VDD+ 0.3 V dc Digital outputs to DGND -0.3 V dc to VDD+ 0.3 V dc Power dissipati

13、on at TA= +75C (PD) 2/ . 450 mW Lead temperature (soldering, 10 seconds) . +300C Storage temperature range . -65C to +150C Thermal resistance, junction-to-case (JC) See MIL-STD-1835 1.4 Recommended operating conditions. Positive supply voltage (VDD) +4.75 V dc to +5.25 V dc Negative supply voltage (

14、VSS) . -4.75 V dc to 5.25 V dc AGND 0 V dc DGND 0 V dc External clock frequency (fCLK) 2.5 MHz Ambient operating temperature range (TA) . -55C to +125C 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of

15、 this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those listed in the issue of the Department of Defense Index of Specifications and Standards (DoDISS) and supplement thereto, cited in the solicitation. SPECIFICATION DEPARTMENT OF DEFENSE MIL

16、-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. STANDARDS DEPARTMENT OF DEFENSE MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. HANDBOOKS DEPARTMENT OF DEFENSE MIL-HDBK-103 - List of Standard Microcir

17、cuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Unless otherwise indicated, copies of the specification, standards, and handbooks are available from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the

18、event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 1/ Stresses above the absolute maximum rating

19、may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2/ Derate linearly at 10 mW/C above TA= +75C.Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAW

20、ING SIZE A 5962-93179 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL B SHEET 4 DSCC FORM 2234 APR 97 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as mod

21、ified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices

22、 and as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outline(s). The case outl

23、ine(s) shall be in accordance with 1.2.4 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and

24、postirradiation parameter limits are as specified in table I and shall apply over the full ambient operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are defined in table

25、 I. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked as listed in MIL-HDBK-103. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marki

26、ng the “5962-“ on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A. 3.5.1 Certification/compliance ma

27、rk. The certification mark for device classes Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. The compliance mark for device class M shall be a “C“ as required in MIL-PRF-38535, appendix A. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be

28、required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6.2 herein). The

29、 certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturers product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appe

30、ndix A and herein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change for device

31、 class M. For device class M, notification to DSCC-VA of change of product (see 6.2 herein) involving devices acquired to this drawing is required for any change as defined in MIL-PRF-38535, appendix A. 3.9 Verification and review for device class M. For device class M, DSCC, DSCCs agent, and the ac

32、quiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing s

33、hall be in microcircuit group number 81 (see MIL-PRF-38535, appendix A).Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-93179 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL B SHEET 5

34、DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions 1/ -55C TA +125C unless otherwise specified Group A subgroups Device type Limits Unit Min Max Resolution RES 1,2,3 All 12 Bits Integral nonlinearity INL 1,2,3 All 1.0 LSB Differential nonlinearity DNL 1,2,3

35、 All 1.0 LSB Bipolar zero error BZE 1,2,3 All 6.0 LSB 1 8.0 Full scale error FSE 2/ 2,3 All 30 LSB Track/hold acquisition time TACQ3/ 9,10,11 All 2.0 s Analog input voltage range VIN1,2,3 All 10 V Analog input current IIN1,2,3 All 600 A REFOUTvoltage VREF1 All 2.99 3.01 V REFOUTvoltage temperature c

36、oefficient VREF/ T 2,3 All 60 ppm/C REFOUTvoltage load sensitivity VREF/ I Reference load current change = 0 to 50 A 4/ 1,2,3 All -1.0 mV Input logic high voltage VINH3/ 1,2,3 All 2.4 V Input logic low voltage VINL3/ 1,2,3 All 0.8 Output logic high voltage VOHISOURCE= 40 A 1,2,3 All 4.0 V Output log

37、ic low voltage VOLISINK= 1.6 mA 1,2,3 All 0.4 V VIN= 0 V to VDD10 Input current IIN12/ 8 /CLK input only, VIN= VSSto VDD1,2,3 All 10 A IDD13 Supply current ISS1,2,3 All 6.0 mA Input capacitance CINSee 4.4.1c 4 All 10 pF DB11 DB0 floating state output capacitance COUTSee 4.4.1c 4 All 15 pF DB11 DB0 f

38、loating state leakage current IL1,2,3 All 10 A See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-93179 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL B SH

39、EET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics Continued. Test Symbol Conditions 1/ -55C TA +125C unless otherwise specified Group A subgroups Device type Limits Unit Min Max External clock conversion time tCONV (ext) fCLK= 2.5 MHz, see figure 2 9,10,11 All 7.2 8.0 s Int

40、ernal clock conversion time tCONV (int) See figure 2 9,10,11 All 6.5 9.0 s CONVST pulse width t15/ 6/ 9 All 50 ns CS to RD setup time (mode 1) t25/ 6/ 9 All 0 ns RD pulse width t35/ 9,10,11 All 75 ns CS to RD hold time (mode 1) t45/ 6/ 9 All 0 ns RD to INT delay time t55/ 6/ 9 All 70 ns Data access

41、time after RD t65/ 7/ 9,10,11 All 70 ns Bus relinquish time after RD t75/ 8/ 9,10,11 All 5.0 50 ns HBEN to RD setup time t85/ 6/ 9 All 0 ns HBEN to RD hold time t95/ 6/ 9 All 0 ns SSTRB to SCLK falling edge setup time t105/ 6/ 9 All 100 ns SCLK cycle time t115/ 6/ 9/ 9 All 370 ns SCLK to valid data

42、delay time t125/ 6/ 10/ 9 All 150 ns SCLK rising edge to SSTRB t135/ 6/ 9 All 20 100 ns Bus relinquish time after SCLK t145/ 6/ 9 All 10 100 ns CS to RD setup time (mode 2) t155/ 6/ 9 All 60 ns Propagation delay time, CS to BUSY t165/ 6/ 9 All 120 ns See footnotes at end of table. Provided by IHSNot

43、 for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-93179 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL B SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics Continued. Test Symb

44、ol Conditions 1/ -55C TA +125C unless otherwise specified Group A subgroups Device type Limits Unit Min Max Data setup time prior to BUSY t175/ 6/ 9 All 200 ns CS to RD hold time (mode 2) t185/ 6/ 9 All 0 ns HBEN to CS setup time t195/ 6/ 9 All 0 ns HBEN to CS setup time t205/ 6/ 9 All 0 ns 1/ VDD=

45、+4.75 V to +5.25 V, VSS= -4.75 V to 5.25 V, AGND = DGND = 0 V, fCLK= 2.5 MHz external. 2/ Includes internal reference error and is calculated after bipolar zero error has been adjusted out. 3/ Guaranteed by dc accuracy test results when used as a setup condition. 4/ Reference load should not be chan

46、ged during conversion. 5/ Input tr , tf= 5.0 ns (10% to 90% of +5.0 V), timing voltage reference level = 1.6 V, see figure 2. 6/ Guaranteed if not tested. 7/ Test t6is defined as the time required for an output to cross 0.8 V or 2.4 V. 8/ Test t7is defined as the time required for the data lines to

47、change 0.5 V. 9/ SCLK mark/space ratio (measured from a voltage level of 1.6 V) is 40/60 to 60/40. 10/ SDATA will drive higher capacitive loads but will add to t12since it increases the external RC time constant (4.7 k | CL) and hence the time to reach 2.4 V, CL= 35 pF. Provided by IHSNot for Resale

48、No reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-93179 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL B SHEET 8 DSCC FORM 2234 APR 97 Device type 01 Case outline L Terminal number Terminal symbol 1 RD 2 BUSY /INT 3 CLK 4 DB11/ HBEN 5 DB10/ SSTRB 6 DB9/SCLK 7 DB8/SDATA 8 DB7/Low 9 DB6/Low10 DB5/Low 11 DB4/Low12 DGND 13 DB3/DB11 14 DB2/DB10 15 DB1/DB9 16 DB0/DB8 17 VDD18 AGND19 REFOUT20 VIN21 VSS22 12/ 8/CLK 23 CONVST 24 CS FIGURE 1. Terminal connections. Prov