DLA SMD-5962-89598 REV R-2006 MICROCIRCUIT MEMORY DIGITAL CMOS 128K X 8 STATIC RANDOM ACCESS MEMORY (SRAM) LOW POWER MONOLITHIC SILICON《硅单片 低功率128K X 8静态随机存取存储器 氧化物半导体数字记忆微型电路》.pdf

《DLA SMD-5962-89598 REV R-2006 MICROCIRCUIT MEMORY DIGITAL CMOS 128K X 8 STATIC RANDOM ACCESS MEMORY (SRAM) LOW POWER MONOLITHIC SILICON《硅单片 低功率128K X 8静态随机存取存储器 氧化物半导体数字记忆微型电路》.pdf》由会员分享，可在线阅读，更多相关《DLA SMD-5962-89598 REV R-2006 MICROCIRCUIT MEMORY DIGITAL CMOS 128K X 8 STATIC RANDOM ACCESS MEMORY (SRAM) LOW POWER MONOLITHIC SILICON《硅单片 低功率128K X 8静态随机存取存储器 氧化物半导体数字记忆微型电路》.pdf（91页珍藏版）》请在麦多课文档分享上搜索。

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED H Add device type 41. Make corrections to case outline N, dimension b. Add vendor CAGE 65786 as source of supply for device type 41. Update boilerplate. Editorial changes throughout. 97-03-26 Raymond Monnin J Add device types 42, 43, 44, 45, and 46

2、. Editorial changes to pages 1, 3, 7-15. Update boilerplate. ksr 98-03-03 Raymond Monnin K Added provisions to accommodate radiation-hardened devices. Added device type 47 to drawing. glg 00-03-01 Raymond Monnin L Corrected case outline 8 Figure 1 to show correct numbering of terminals. Corrected Fi

3、gure 2 Terminal connections. Corrected the case outline Y Figure 1 to show the proper distance of E and E1. Added note to Case outline Y Figure 1, to allow for bottom brazed package as an alternative style to the side brazed package . Update boilerplate. Editorial changes throughout. ksr 00-12-08 Ra

4、ymond Monnin M Changed the minimum value for the Q dimension on package T from 0.026 to 0.020 and removed footnote 12. Editorial changes throughout ksr 02-12-19 Raymond Monnin N Added device type 48 to drawing. ksr 03-08-12 Raymond Monnin P Corrected typo on Figure 4 (Read Cycle). ksr 05-08-16 Raymo

5、nd Monnin R Vendor requested change in capacitance in Table I for devices 39 and 40 from 5 pF to 8 pF. ksr 06-02-13 Raymond Monnin REV R R R R R R R R R R R R R R R R R R SHEET 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 REV R R R R R R R R R R R R R R R R R R R R SHEET 15 16 17 18 19 20 2

6、1 22 23 24 25 26 27 28 29 30 31 32 33 34 REV STATUS REV R R R R R R R R R R R R R R OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Kenneth S. Rice STANDARD MICROCIRCUIT DRAWING CHECKED BY Raymond Monnin DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 http:/www.dscc.dl

7、a.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Michael A. Frye AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 89-04-21 MICROCIRCUIT, MEMORY, DIGITAL, CMOS, 128K X 8 STATIC RANDOM ACCESS MEMORY (SRAM) LOW POWER, MONOLITHIC SILICON AMSC N/A REVISION LEVEL R SIZ

8、E A CAGE CODE 67268 5962-89598 SHEET 1 OF 52 DSCC FORM 2233 APR 97 5962-E261-06 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89598 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL R

9、SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Ident

10、ifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 - 89598 01 M X A Federal RHA Device Device Case Lead stock class designator type class outline finish designator (see 1.2.1

11、) (see 1.2.2) designator (see 1.2.4) (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, ap

12、pendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number 1/ Circuit function Access time 01 128K x 8 low power CMOS SRAM 120 n

13、s 02 128K x 8 low power CMOS SRAM 100 ns 03 128K x 8 low power CMOS SRAM 85 ns 04 128K x 8 low power CMOS SRAM 70 ns 05 128K x 8 low power CMOS SRAM 120 ns 06 128K x 8 low power CMOS SRAM 100 ns 07 128K x 8 low power CMOS SRAM 85 ns 08 128K x 8 low power CMOS SRAM 70 ns 09 128K x 8 low power CMOS SR

14、AM 55 ns 10 128K x 8 low power CMOS SRAM 45 ns 11 128K x 8 low power CMOS SRAM 35 ns 12 128K x 8 low power CMOS SRAM 25 ns 13 128K x 8 low power CMOS SRAM dual CE 120 ns 14 128K x 8 low power CMOS SRAM dual CE 100 ns 15 128K x 8 low power CMOS SRAM dual CE 85 ns 16 128K x 8 low power CMOS SRAM dual

15、CE 70 ns 17 128K x 8 low power CMOS SRAM dual CE 55 ns 18 128K x 8 low power CMOS SRAM dual CE 45 ns 19 128K x 8 low power CMOS SRAM dual CE 35 ns 20 128K x 8 low power CMOS SRAM dual CE 25 ns 21 128K x 8 low power CMOS SRAM dual CE 20 ns 22 128K x 8 standard power CMOS SRAM 120 ns 23 128K x 8 stand

16、ard power CMOS SRAM 100 ns 24 128K x 8 standard power CMOS SRAM 85 ns 25 128K x 8 standard power CMOS SRAM 70 ns 26 128K x 8 standard power CMOS SRAM 55 ns 27 128K x 8 standard power CMOS SRAM 45 ns 28 128K x 8 standard power CMOS SRAM 35 ns 29 128K x 8 standard power CMOS SRAM 25 ns 30 128K x 8 sta

17、ndard power CMOS SRAM dual CE 120 ns 31 128K x 8 standard power CMOS SRAM dual CE 100 ns 1/ Generic numbers are listed on the Standard Microcircuit Drawing Source Approval Bulletin at the end of this document and will also be listed in MIL-HDBK-103. Provided by IHSNot for ResaleNo reproduction or ne

18、tworking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89598 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL R SHEET 3 DSCC FORM 2234 APR 97 Device type Generic number 1/ Circuit function Access time 32 128K x 8 standard power CMOS SRAM dual

19、 CE 85 ns 33 128K x 8 standard power CMOS SRAM dual CE 70 ns 34 128K x 8 standard power CMOS SRAM dual CE 55 ns 35 128K x 8 standard power CMOS SRAM dual CE 45 ns 36 128K x 8 standard power CMOS SRAM dual CE 35 ns 37 128K x 8 standard power CMOS SRAM dual CE 25 ns 38 128K x 8 standard power CMOS SRA

20、M dual CE 20 ns 39 128K x 8 standard power CMOS SRAM 20 ns 40 128K x 8 low power CMOS SRAM 20 ns 41 128K x 8 standard power CMOS SRAM dual CE 15 ns 42 128K x 8 low power CMOS SRAM 70 ns 43 128K x 8 standard power CMOS SRAM 70 ns 44 128K x 8 standard power CMOS SRAM 15 ns 45 128K x 8 standard power C

21、MOS SRAM dual CE 12 ns 46 128K x 8 standard power CMOS SRAM 12 ns 47 128K x 8 very low power CMOS SRAM 30 ns 48 128K x 8 low power CMOS SRAM 15 ns 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device req

22、uirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outlines. The case outlines are as designated in MIL-

23、STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style X GDIP1-T32 or CDIP2-T32 32 dual-in-line Y 2/ See figure 1 32 SOJ package Z See figure 1 32 dual-in-line U See figure 1 32 rectangular chip carrier T See figure 1 32 flat pack N See figure 1 32 rectangular chip ca

24、rrier M CQCC1-N32 32 rectangular chip carrier 9 See figure 1 32 J-leaded rectangular chip carrier 8 See figure 1 32 zig-zag in-line 7 See figure 1 32 SOJ package 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device cla

25、ss M. 1.3 Absolute maximum ratings. 3/ 4/ Supply voltage range (VCC). -0.5 V dc to +7.0 V dc DC input voltage range (VIN) . -0.5 V dc to VCC+0.5 V dc 5/ DC output voltage range (VOUT). -0.5 V dc to VCC+0.5 V dc 5/ Storage temperature range -65C to +150C Maximum power dissipation (PD). 1.0 W Lead tem

26、perature (soldering, 10 seconds). +260C 1/ Generic numbers are listed on the Standard Microcircuit Drawing Source Approval Bulletin at the end of this document and will also be listed in MIL-HDBK-103. 2/ A bottom brazed option for this package now exists (See figure 1, case outline Y NOTE:). Custome

27、rs may specify in the purchase order to negate the option as acceptable for their use. 3/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 4/ All voltages referenced to VSS(VS

28、S= ground) unless otherwise specified. 5/ Negative undershoots to a minimum of -3.0 V are allowed with a maximum of 20 ns pulse width. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89598 DEFENSE SUPPLY CENT

29、ER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL R SHEET 4 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings - continued. 3/ 4/ Thermal resistance, junction-to-case (JC): Case M See MIL-STD-1835 Cases X, Y, Z, U, and 7 . 11C/W 6/ Cases T, N, and 9 10C/W 6/ Case 8 . 16C/W 6/ Output voltage appli

30、ed in high Z state -0.5 V dc to VCC+0.5 V dc Maximum power dissipation, (PD) 1.0 W Maximum junction temperature (TJ) +150C 7/ 1.4 Recommended operating conditions. Supply voltage range (VCC) 4.5 V dc minimum to 5.5 V dc maximum Supply voltage range (VSS). 0.0 V dc High level input voltage range (VIH

31、). 2.2 V dc to VCC+ 0.5 V dc Low level input voltage range (VIL) -0.5 V dc to 0.8 V dc Case operating temperature range (TC) -55C to +125C 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing

32、 to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 -

33、 Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/as

34、sist.daps.dla.mil/quicksearch/ or http:/assist.daps.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein. Unless o

35、therwise specified, the issues of the documents are the issues of the documents cited in the solicitation. AMERICAN SOCIETY FOR TESTING AND MATERIALS (ASTM) ASTM Standard F1192-95 - Standard Guide for the Measurement of Single Event Phenomena from Heavy Ion Irradiation of Semiconductor Devices. (App

36、lications for copies of ASTM publications should be addressed to: ASTM International, PO Box C700, 100 Barr Harbor Drive, West Conshohocken, PA 19428-2959; http:/www.astm.org.) (Non-Government standards and other publications are normally available from the organizations that prepare or distribute t

37、he documents. These documents also may be available in or through libraries or other informational services.) 3/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 4/ All voltag

38、es referenced to VSS(VSS= ground) unless otherwise specified. 6/ When the JCfor this case is specified in MIL-STD-1835, that value shall supersede the value indicated herein. 7/ Maximum junction temperature may be increased to +175C during burn-in and steady-state life. Provided by IHSNot for Resale

39、No reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89598 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL R SHEET 5 DSCC FORM 2234 APR 97 ELECTRONICS INDUSTRIES ASSOCIATION (EIA) JEDEC Standard EIA/JESD78 - IC Latch-U

40、p Test. (Applications for copies should be addressed to the Electronics Industries Association, 2500 Wilson Boulevard, Arlington, VA 22201; http:/www.jedec.org.) 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this dra

41、wing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 and as spec

42、ified herein or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN

43、 class level B devices and as specified herein. 3.1.1 Microcircuit die. For the requirements of microcircuit die, see appendix C to this document. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein fo

44、r device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.4 herein and figure 1. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2. 3.2.3 Truth table. The truth

45、table shall be as specified on figure 3. 3.2.4 Functional tests. Various functional tests used to test this device are contained in the appendix. If the test patterns cannot be implemented due to test equipment limitations, alternate test patterns to accomplish the same results shall be allowed. For

46、 device class M, alternate test patterns shall be maintained under document revision level control by the manufacturer and shall be made available to the preparing or acquiring activity upon request. For device classes Q and V alternate test patterns shall be under the control of the device manufact

47、urers Technology Review Board (TRB) in accordance with MIL-PRF-38535 and shall be made available to the preparing or acquiring activity upon request. 3.2.5 Die overcoat. Polyimide and silicone coatings are allowable as an overcoat on the die for alpha particle protection only. Each coated microcircu

48、it inspection lot (see inspection lot as defined in MIL-PRF-38535) shall be subjected to and pass the internal moisture content test at 5000 ppm (see method 1018 of MIL-STD-883). The frequency of the internal water vapor testing shall not be decreased unless approved by the preparing activity for class M. The TRB will ascertain the requirements as pr