DLA SMD-5962-86875 REV D-2006 MICROCIRCUIT MEMORY DIGITAL CMOS 1K X 8 DUAL PORT STATIC RANDOM ACCESS MEMORY (SRAM) MONOLITHIC SILICON《硅单块 1KX8双口静态随机存取存储器 互补金属氧化物半导体 数字主储存器微型电路》.pdf

《DLA SMD-5962-86875 REV D-2006 MICROCIRCUIT MEMORY DIGITAL CMOS 1K X 8 DUAL PORT STATIC RANDOM ACCESS MEMORY (SRAM) MONOLITHIC SILICON《硅单块 1KX8双口静态随机存取存储器 互补金属氧化物半导体 数字主储存器微型电路》.pdf》由会员分享，可在线阅读，更多相关《DLA SMD-5962-86875 REV D-2006 MICROCIRCUIT MEMORY DIGITAL CMOS 1K X 8 DUAL PORT STATIC RANDOM ACCESS MEMORY (SRAM) MONOLITHIC SILICON《硅单块 1KX8双口静态随机存取存储器 互补金属氧化物半导体 数字主储存器微型电路》.pdf（32页珍藏版）》请在麦多课文档分享上搜索。

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Add case outline “U“ to the drawing. Change to parameter tWHAX of table I. Editorial change throughout. 89-10-30 Michael A. Frye B Changes in accordance with NOR 5962-R004-91 91-09-20 Michael A. Frye C Redrawn with changes. Added device types 19

2、through 22. Added vendor CAGE 65786 for device types 19 and 20 Added vendor CAGE 61772 for devices 21 and 22. Corrected errors to Table I. Added pin 1 reference to case outline U. Editorial changes throughout. 93-04-28 Michael A. Frye D Boilerplate update, part of 5 year review. ksr 06-08-08 Raymond

3、 Monnin THE ORIGINAL FIRST PAGE OF THIS DRAWING HAS BEEN REPLACED. REV SHET REV D D D D D D D D D D D D D SHEET 15 16 17 18 19 20 21 22 23 24 25 26 27 REV STATUS REV D D D D D D D D D D D D D D OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY James E. Jamison DEFENSE SUPPLY CENT

4、ER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY Charles Reusing COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Michael A. Frye AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 88-05-11 MICROCIRCUIT, MEMORY, DIGITA

5、L, CMOS, 1K X 8 DUAL PORT STATIC RANDOM ACCESS MEMORY (SRAM), MONOLITHIC SILICON AMSC N/A REVISION LEVEL D SIZE A CAGE CODE 67268 5962-86875 SHEET 1 OF 27 DSCC FORM 2233 APR 97 5962-E530-06 .Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MI

6、CROCIRCUIT DRAWING SIZE A 5962-86875 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535,

7、 appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-86875 01 X A Drawing number Device type (see 1.2.1) Case outline(see 1.2.2) Lead finish(see 1.2.3)1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Device t

8、ype Generic number 1/ Circuit function Access time 01 1K x 8 bit dual port CMOS SRAM (Master) 90 ns 02 1K x 8 bit dual port CMOS SRAM (Master) 70 ns 03 1K x 8 bit dual port CMOS SRAM (Master) 55 ns 04 1K x 8 bit dual port CMOS SRAM (Master) 45 ns 05 1K x 8 bit dual port CMOS SRAM (Master) 90 ns (dat

9、a retention) 06 1K x 8 bit dual port CMOS SRAM (Master) 70 ns (data retention) 07 1K x 8 bit dual port CMOS SRAM (Master) 55 ns (data retention) 08 1K x 8 bit dual port CMOS SRAM (Master) 45 ns (data retention) 09 1K x 8 bit dual port CMOS SRAM (Slave) 90 ns 10 1K x 8 bit dual port CMOS SRAM (Slave)

10、 70 ns 11 1K x 8 bit dual port CMOS SRAM (Slave) 55 ns 12 1K x 8 bit dual port CMOS SRAM (Slave) 45 ns 13 1K x 8 bit dual port CMOS SRAM (Slave) 90 ns (data retention) 14 1K x 8 bit dual port CMOS SRAM (Slave) 70 ns (data retention) 15 1K x 8 bit dual port CMOS SRAM (Slave) 55 ns (data retention) 16

11、 1K x 8 bit dual port CMOS SRAM (Slave) 45 ns (data retention) 17 1K x 8 bit dual port CMOS SRAM (Master) 35 ns 18 1K x 8 bit dual port CMOS SRAM (Slave) 35 ns 19 1K x 8 bit dual port CMOS SRAM (Master) 35 ns 20 1K x 8 bit dual port CMOS SRAM (Slave) 35 ns 21 1K x 8 bit dual port CMOS SRAM (Master)

12、35 ns (data retention) 22 1K x 8 bit dual port CMOS SRAM (Slave) 35 ns (data retention) 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style X GDIP1-T48 or CDIP2-T48 48 dual-in-line Y See figure 1 4

13、8 square leadless chip carrier Z CQCC1-N52 52 square leadless chip carrier U See figure 1 48 flat pack 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1/ Generic numbers are listed on the Standardized Military Drawing Source Approval Bulletin at the end of this docum

14、ent and will also be listed in MIL-HDBK-103. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86875 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 3 DSCC FORM 2234 APR 97 1.3 A

15、bsolute maximum ratings. 2/ Supply voltage range (VCC) .-0.5 V dc to +7.0 V dc Input voltage range .-0.5 V dc to +7.0 V dc Output sink current50 mA Output short circuit duration10 seconds Power dissipation (PD) 1.5 W Thermal resistance, junction-to-case (JC): Case X.30C/W 3/ Case Y and U 12C/W 3/ Ca

16、se Z.See MIL-STD-1835 Junction temperature +150C 4/ Temperature under bias-55C to +125C Storage temperature range .-65C to +150C Lead temperature (soldering, 10 seconds)+300C 1.4 Recommended operating conditions. 2/ Supply voltage range (VCC) .4.5 V dc to 5.5 V dc Case operating temperature range (T

17、C) -55C to +125C Minimum input high voltage level (VIH)2.2 V Maximum input low voltage level (VIL).0.8 V 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. U

18、nless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuit

19、s. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/assist.daps.dla.mil/quicksearch/ or

20、http:/assist.daps.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. N

21、othing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 2/ Unless otherwise specified, all voltages are referenced to ground (GND). 3/ When a thermal resistance value for this case outline is included in MIL-STD-1835, that value sha

22、ll supersede the value specified herein. 4/ Maximum junction temperature may be increased to 175C during the burn-in and steady state life test. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86875 DEFENSE S

23、UPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 4 DSCC FORM 2234 APR 97 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to thi

24、s drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activ

25、ity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herei

26、n. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Ca

27、se outlines. The case outlines shall be in accordance with 1.2.2 herein and figure 1. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2. 3.2.3 Truth tables. The truth tables shall be as specified on figure 3. 3.2.4 Block diagram. The block diagram shall be as spe

28、cified on figure 4. 3.2.5 Die overcoat. Polyimide and silicone coatings are allowable as an overcoat on the die for alpha particle protection only. Each coated microcircuit inspection lot (see inspection lot as defined in MIL-PRF-38535) shall be subjected to and pass the internal moisture content te

29、st at 5000 ppm (see method 1018 of MIL-STD-883). The frequency of the internal water vapor testing shall not be decreased unless approved by the preparing activity for class M. The TRB will ascertain the requirements as provided by MIL-PRF-38535 for classes Q and V. Samples may be pulled any time af

30、ter seal. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be

31、the subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For pac

32、kages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-3

33、8535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be liste

34、d as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Cer

35、tificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DSCC-VA shall be required for any change that affects this drawing. 3.9 Ver

36、ification and review. DSCC, DSCCs agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. Provided by IHSNot for ResaleNo reproduction or netw

37、orking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86875 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Limits Test Symbol Conditions 1/ 2/ -55C TC +125C 4.5

38、 V VCC 5.5 V unless otherwise specified Group A subgroups Device type Min Max Unit High level output voltage VOHIO= -4.0 mA, VIH= 2.2 V, VIL= 0.8 V 1, 2, 3 All 2.4 V Low level output voltage (I/O0- I/O7terminals only) VOL1IO= 4.0 mA, VIH= 2.2 V, VIL= 0.8 V 1, 2, 3 All 0.4 V Low level open drain outp

39、ut voltage (BUSYL, BUSYR, INTL, and INTRterminals only) VOL2IO= 16 mA 1, 2, 3 All 0.5 V High impedance output leakage current IOZCE = VIH, VO= GND to VCC1, 2, 3 All -10.0 10.0 A High level input voltage VIH1, 2, 3 All 2.2 V Low level input voltage VIL1, 2, 3 All 0.8 V IIHVIH= 5.5 V 1, 2, 3 All 10.0

40、A Input leakage current IILVIL= GND 1, 2, 3 All -10.0 A 01-04, 09-12, 19-20 65 06-08, 14-16 55 05, 13, 17, 18 45 ISB1CEL= CE R VIH, both ports standby, VCC= 5.5 V 1, 2, 3 21, 22 60 mA 02- 04, 10-12 135 01, 09, 19, 20 125 06-08, 14-16 110 05, 13, 17, 18 100 Operating supply current (standby) ISB2CEL=

41、 CE R VIH, one port standby, active port outputs open, VCC= 5.5 V 1, 2, 3 21, 22 150 mA See footnotes a end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86875 DEFENSE SUPPLY CENTER COLUMBUS COLUM

42、BUS, OHIO 43218-3990 REVISION LEVEL D SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Limits Test Symbol Conditions 1/ 2/ -55C TC +125C 4.5 V VCC 5.5 V unless otherwise specified Group A subgroups Device type Min Max Unit 01-04, 09-12, 17-20 30 ISB3CEL= CE

43、R VCC- 0.2 V, VCC= 5.5 V, VIN 0.2 V or VIN VCC- 0.2 V, both ports full standby 1, 2, 3 05-08, 13-16, 21, 22 10 mA 21, 22 140 04, 12 125 03, 11 120 02, 10 115 01, 09, 19, 20 110 08, 16 95 07, 15 90 06, 14 85 Operating supply current (full standby) ISB4CEL= CE R VCC- 0.2 V, VCC= 5.5 V, VIN 0.2 V or VI

44、N VCC- 0.2 V, one ports full standby, active port outputs open 1, 2, 3 05, 13, 17, 18 80 mA 03, 04, 11, 12, 21, 22 230 02, 10 225 01, 09 200 07, 08, 15, 16 185 06, 14, 19, 20 180 05, 13 160 Operating supply current (dynamic) ICCCEL= CE R= VIL, VCC= 5.5 V, f = 1MHz, both ports active 1, 2, 3 17, 18 1

45、50 mA VCCfor data retention VDR1, 2, 3 05-08, 13-16, 21, 22 2.0 V Data retention current ICCDRVCC= 2.0 V, CE VCC- 0.2 V, VIN VCC- 0.2 V or VIN 0.2 V 1, 2, 3 05-08, 13-16, 21, 22 4.0 mA Chip deselect to data retention time 3/ tCDRVCC= 2.0 V, CE VCC- 0.2 V, VIN VCC- 0.2 V or VIN 0.2 V 1, 2, 3 05-08, 1

46、3-16, 21, 22 0 ns 05, 13 90 06, 14 70 07, 15 55 08, 16 45 Operation recovery time 3/ tRVCC= 2.0 V, CE VCC- 0.2 V, VIN VCC- 0.2 V or VIN 0.2 V 1, 2, 3 21, 22 35 ns See footnotes a end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD

47、MICROCIRCUIT DRAWING SIZE A 5962-86875 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Limits Test Symbol Conditions 1/ 2/ -55C TC +125C 4.5 V VCC 5.5 V unless otherwise specified Gro

48、up A subgroups Device type Min Max Unit Input capacitance 4/ 5/ CINf = 1 MHz, VIN= VCCor GND, see 4.3.1c, TA= 25C 4 All 12 pF 01-20 10 Output capacitance 4/ 5/ COUTf = 1 MHz, VIN= VCCor GND, see 4.3.1c, TA= 25C 4 21, 22 11 pF Functional tests See 4.3.1d 7, 8A, 8B All Read cycle 17-22 35 04, 08, 12,

49、16 45 01, 05, 09, 13 90 02, 06, 10, 14 70 Read cycle time tAVAV6/ 9, 10, 11 03, 07, 11, 15 55 ns 17-22 35 04, 08, 12, 16 45 01, 05, 09, 13 90 02, 06, 10, 14 70 Address access time tAVQV6/ 9, 10, 11 03, 07, 11, 15 55 ns 17, 18 3 01, 05, 09, 13 10 Output hold from address change tAXQX6/ 9, 10, 11 02-04