DLA DSCC-VID-V62 10615-2010 MICROCIRCUIT LINEAR CMOS SPDT SWITCH MONOLITHIC SILICON.pdf
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1、 REVISIONSLTR DESCRIPTION DATE APPROVEDPrepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PMIC N/A PREPARED BY RICK OFFICER DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 Original date of drawing YY-MM-DD CH
2、ECKED BY RAJESH PITHADIA TITLE MICROCIRCUIT, LINEAR, CMOS SPDT SWITCH, MONOLITHIC SILICON 10-09-08 APPROVED BY CHARLES F. SAFFLE SIZE A CODE IDENT. NO. 16236 DWG NO. V62/10615 REV PAGE 1 OF 15 AMSC N/A 5962-V066-10 Provided by IHSNot for ResaleNo reproduction or networking permitted without license
3、from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/10615 REV PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance CMOS single pole double throw (SPDT) switch microcircuit, with an operating temperature range of -55C t
4、o +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/10615 - 01 X A Drawing Device type Case outline Lea
5、d finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 ADG419-EP CMOS SPDT switch 1.2.2 Case outline(s). The case outline(s) are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 8 MO-187-AA Plastic surface moun
6、t1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacture: Finish designator Material A Hot solder dip B Tin-lead plateC Gold plateD PalladiumE Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking pe
7、rmitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/10615 REV PAGE 3 1.3 Absolute maximum ratings. 1/ Positive power supply (VDD) to negative power supply (VSS) 44 V VDDto ground (GND) . -0.3 V to +25 V VSSto GND . +0.3 V to -25 V Logic p
8、ower supply (VL) to GND -0.3 V to VDD+ 0.3 V Analog, digital inputs 2/ VSS- 2 V to VDD+ 2 V or 30 mA, whichever comes first Continuous current, source terminal (S) or drain terminal (D) . 30 mA Peak current, S or D (pulsed at 1 ms, 10% duty cycle maximum) 100 mA Power dissipation (PD) . 315 mW Junct
9、ion temperature range (TJ) 150C Storage temperature range (TSTG) . -65C to +150C Electrostatic discharge (ESD) rating 3/ Thermal resistance, junction to case (JC): 44C/W Thermal impedance, junction to ambient (JA) 205C/W 1.4 Recommended operating conditions. 4/ Operating free-air temperature range (
10、TA) . -55C to +125C 1/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
11、implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ Overvoltages at IN, S or D is clamped by internal diodes. Limit current to the maximum ratings given. 3/ The electrostatic discharge limit will be specified when available from the manufactu
12、rer. 4/ Use of this product beyond the manufacturers design rules or stated parameters is done at the users risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. Provided by IHSNot for ResaleNo reproduction or networking permitte
13、d without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/10615 REV PAGE 4 2. APPLICABLE DOCUMENTS JEDEC PUB 95 Registered and Standard Outlines for Semiconductor Devices (Applications for copies should be addressed to the Electronic Industries Allia
14、nce, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or online at http:/www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C.
15、 ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as s
16、pecified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal
17、connections shall be as shown in figure 2. 3.5.3 Truth table. The truth table shall be as shown in figure 3. 3.5.4 Timing waveforms and test circuit. The timing waveforms and test circuits shall be as shown in figures 4 through 10. Provided by IHSNot for ResaleNo reproduction or networking permitted
18、 without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/10615 REV PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions 2/Temperature, TA Device type Limits Unit Min Max Dual supply Analog switch Analog signal range -55C
19、to +125C 01 VSSto VDDV On resistance RONVD= 12.5 V, IS= -10 mA, +25C 01 35 VDD= +13.5 V, VSS= -13.5, see figure 4 -55C to +125C 45 Leakage currents VDD= +16.5 V, VSS= -16.5 V Source off leakage current IS(off) VD= 15.5 V, VS= 15.5 V, +25C 01 0.25 nA see figure 5 -55C to +125C 15 Drain off leakage cu
20、rrent ID(off) VD= 15.5 V, VS= 15.5 V, +25C 01 0.75 nA see figure 5 -55C to +125C 30 Channel on leakage current ID, ISVS= VD= 15.5 V, +25C 01 0.75 nA (on) see figure 6 -55C to +125C 30 Digital inputs Input high voltage VINH-55C to +125C 01 2.4 V Input low voltage VINL-55C to +125C 01 0.8 V Input curr
21、ent IINLor IINHVIN= VINLor VINH-55C to +125C 01 0.5 A See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/10615 REV PAGE 6 TABLE I. Electrical per
22、formance characteristics Continued. 1/ Test Symbol Conditions 2/Temperature, TA Device type Limits Unit Min Max Dual supply - continued. Dynamic characteristics 3/ Transition timing tTRL= 300 , CL= 35 pF, +25C 01 145 ns VS1= 10 V, VS2= 10 V, see figure 7 -55C to +125C 200 Break-before-make time dela
23、y tDRL= 300 , CL= 35 pF, VS1= VS2= 10 V, see figure 8 +25C 01 5 ns Off isolation RL= 50 , f = 1 MHz, see figure 9 +25C 01 80 typical dB Channel-to-channel crosstalk RL= 50 , f = 1 MHz, see figure 10 +25C 01 90 typical dB Source capacitance CS(off) f = 1 MHz +25C 01 6 typical pF Drain capacitance CD,
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