欢迎来到麦多课文档分享! | 帮助中心 海量文档,免费浏览,给你所需,享你所想!
麦多课文档分享
全部分类
  • 标准规范>
  • 教学课件>
  • 考试资料>
  • 办公文档>
  • 学术论文>
  • 行业资料>
  • 易语言源码>
  • ImageVerifierCode 换一换
    首页 麦多课文档分享 > 资源分类 > PDF文档下载
    分享到微信 分享到微博 分享到QQ空间

    DLA DSCC-VID-V62 10615-2010 MICROCIRCUIT LINEAR CMOS SPDT SWITCH MONOLITHIC SILICON.pdf

    • 资源ID:689315       资源大小:109.58KB        全文页数:15页
    • 资源格式: PDF        下载积分:10000积分
    快捷下载 游客一键下载
    账号登录下载
    微信登录下载
    二维码
    微信扫一扫登录
    下载资源需要10000积分(如需开发票,请勿充值!)
    邮箱/手机:
    温馨提示:
    如需开发票,请勿充值!快捷下载时,用户名和密码都是您填写的邮箱或者手机号,方便查询和重复下载(系统自动生成)。
    如需开发票,请勿充值!如填写123,账号就是123,密码也是123。
    支付方式: 支付宝扫码支付    微信扫码支付   
    验证码:   换一换

    加入VIP,交流精品资源
     
    账号:
    密码:
    验证码:   换一换
      忘记密码?
        
    友情提示
    2、PDF文件下载后,可能会被浏览器默认打开,此种情况可以点击浏览器菜单,保存网页到桌面,就可以正常下载了。
    3、本站不支持迅雷下载,请使用电脑自带的IE浏览器,或者360浏览器、谷歌浏览器下载即可。
    4、本站资源下载后的文档和图纸-无水印,预览文档经过压缩,下载后原文更清晰。
    5、试题试卷类文档,如果标题没有明确说明有答案则都视为没有答案,请知晓。

    DLA DSCC-VID-V62 10615-2010 MICROCIRCUIT LINEAR CMOS SPDT SWITCH MONOLITHIC SILICON.pdf

    1、 REVISIONSLTR DESCRIPTION DATE APPROVEDPrepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PMIC N/A PREPARED BY RICK OFFICER DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 Original date of drawing YY-MM-DD CH

    2、ECKED BY RAJESH PITHADIA TITLE MICROCIRCUIT, LINEAR, CMOS SPDT SWITCH, MONOLITHIC SILICON 10-09-08 APPROVED BY CHARLES F. SAFFLE SIZE A CODE IDENT. NO. 16236 DWG NO. V62/10615 REV PAGE 1 OF 15 AMSC N/A 5962-V066-10 Provided by IHSNot for ResaleNo reproduction or networking permitted without license

    3、from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/10615 REV PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance CMOS single pole double throw (SPDT) switch microcircuit, with an operating temperature range of -55C t

    4、o +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/10615 - 01 X A Drawing Device type Case outline Lea

    5、d finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 ADG419-EP CMOS SPDT switch 1.2.2 Case outline(s). The case outline(s) are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 8 MO-187-AA Plastic surface moun

    6、t1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacture: Finish designator Material A Hot solder dip B Tin-lead plateC Gold plateD PalladiumE Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking pe

    7、rmitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/10615 REV PAGE 3 1.3 Absolute maximum ratings. 1/ Positive power supply (VDD) to negative power supply (VSS) 44 V VDDto ground (GND) . -0.3 V to +25 V VSSto GND . +0.3 V to -25 V Logic p

    8、ower supply (VL) to GND -0.3 V to VDD+ 0.3 V Analog, digital inputs 2/ VSS- 2 V to VDD+ 2 V or 30 mA, whichever comes first Continuous current, source terminal (S) or drain terminal (D) . 30 mA Peak current, S or D (pulsed at 1 ms, 10% duty cycle maximum) 100 mA Power dissipation (PD) . 315 mW Junct

    9、ion temperature range (TJ) 150C Storage temperature range (TSTG) . -65C to +150C Electrostatic discharge (ESD) rating 3/ Thermal resistance, junction to case (JC): 44C/W Thermal impedance, junction to ambient (JA) 205C/W 1.4 Recommended operating conditions. 4/ Operating free-air temperature range (

    10、TA) . -55C to +125C 1/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

    11、implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ Overvoltages at IN, S or D is clamped by internal diodes. Limit current to the maximum ratings given. 3/ The electrostatic discharge limit will be specified when available from the manufactu

    12、rer. 4/ Use of this product beyond the manufacturers design rules or stated parameters is done at the users risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. Provided by IHSNot for ResaleNo reproduction or networking permitte

    13、d without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/10615 REV PAGE 4 2. APPLICABLE DOCUMENTS JEDEC PUB 95 Registered and Standard Outlines for Semiconductor Devices (Applications for copies should be addressed to the Electronic Industries Allia

    14、nce, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or online at http:/www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C.

    15、 ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as s

    16、pecified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal

    17、connections shall be as shown in figure 2. 3.5.3 Truth table. The truth table shall be as shown in figure 3. 3.5.4 Timing waveforms and test circuit. The timing waveforms and test circuits shall be as shown in figures 4 through 10. Provided by IHSNot for ResaleNo reproduction or networking permitted

    18、 without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/10615 REV PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions 2/Temperature, TA Device type Limits Unit Min Max Dual supply Analog switch Analog signal range -55C

    19、to +125C 01 VSSto VDDV On resistance RONVD= 12.5 V, IS= -10 mA, +25C 01 35 VDD= +13.5 V, VSS= -13.5, see figure 4 -55C to +125C 45 Leakage currents VDD= +16.5 V, VSS= -16.5 V Source off leakage current IS(off) VD= 15.5 V, VS= 15.5 V, +25C 01 0.25 nA see figure 5 -55C to +125C 15 Drain off leakage cu

    20、rrent ID(off) VD= 15.5 V, VS= 15.5 V, +25C 01 0.75 nA see figure 5 -55C to +125C 30 Channel on leakage current ID, ISVS= VD= 15.5 V, +25C 01 0.75 nA (on) see figure 6 -55C to +125C 30 Digital inputs Input high voltage VINH-55C to +125C 01 2.4 V Input low voltage VINL-55C to +125C 01 0.8 V Input curr

    21、ent IINLor IINHVIN= VINLor VINH-55C to +125C 01 0.5 A See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/10615 REV PAGE 6 TABLE I. Electrical per

    22、formance characteristics Continued. 1/ Test Symbol Conditions 2/Temperature, TA Device type Limits Unit Min Max Dual supply - continued. Dynamic characteristics 3/ Transition timing tTRL= 300 , CL= 35 pF, +25C 01 145 ns VS1= 10 V, VS2= 10 V, see figure 7 -55C to +125C 200 Break-before-make time dela

    23、y tDRL= 300 , CL= 35 pF, VS1= VS2= 10 V, see figure 8 +25C 01 5 ns Off isolation RL= 50 , f = 1 MHz, see figure 9 +25C 01 80 typical dB Channel-to-channel crosstalk RL= 50 , f = 1 MHz, see figure 10 +25C 01 90 typical dB Source capacitance CS(off) f = 1 MHz +25C 01 6 typical pF Drain capacitance CD,

    24、 CS(on) f = 1 MHz +25C 01 55 typical pF Power requirements VDD= +16.5 V, VSS= -16.5 V Drain current IDDVIN= 0 V to 5 V +25C 01 1 A -55C to +125C 2.5 Source current ISS+25C 01 1 A -55C to +125C 2.5 Load current ILVL= 5.5 V +25C 01 1 A -55C to +125C 2.5 See footnotes at end of table. Provided by IHSNo

    25、t for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/10615 REV PAGE 7 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions 4/Temperature, TA Device type Limits Unit Min Max

    26、Single supply Analog switch Analog signal range -55C to +125C 01 0 to VDDV On resistance RONVD= 3 V, 8.5 V, IS= -10 mA, VDD= 10.8 V, see figure 4 -55C to +125C 01 70 Leakage currents VDD= +13.2 V Source off leakage current IS(off) VD= 12.2 V/1 V, VS= 1 V/12.2 V, +25C 01 0.25 nA see figure 5 -55C to

    27、+125C 15 Drain off leakage current ID(off) VD= 12.2 V/1 V, VS= 1 V/12.2 V, +25C 01 0.75 nA see figure 5 -55C to +125C 30 Channel on leakage current ID, ISVS= VD= 12.2 V/1 V, +25C 01 0.75 nA (on) see figure 6 -55C to +125C 30 Digital inputs Input high voltage VINH-55C to +125C 01 2.4 V Input low volt

    28、age VINL-55C to +125C 01 0.8 V Input current IINLor IINHVIN= VINLor VINH-55C to +125C 01 0.5 A See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62

    29、/10615 REV PAGE 8 TABLE I. Electrical performance characteristics Continued. 1/ Test Symbol Conditions 4/Temperature, TA Device type Limits Unit Min Max Single supply - continued. Dynamic characteristics 3/ Transition timing tTRL= 300 , CL= 35 pF, +25C 01 170 ns VS1= 0 V/8 V, VS2= 8 V/0 V, see figur

    30、e 7 -55C to +125C 250 Break-before-make time delay tDRL= 300 , CL= 35 pF, VS1= VS2= 8 V, see figure 8 +25C 01 60 typical ns Off isolation RL= 50 , f = 1 MHz, see figure 9 +25C 01 80 typical dB Channel-to-channel crosstalk RL= 50 , f = 1 MHz, see figure 10 +25C 01 70 typical dB Source capacitance CS(

    31、off) f = 1 MHz +25C 01 13 typical pF Drain capacitance CD, CS(on) f = 1 MHz +25C 01 65 typical pF Power requirements VDD= +13.2 V Drain current IDDVIN= 0 V to 5 V +25C 01 1 A -55C to +125C 2.5 Load current ILVL= 5.5 V +25C 01 1 A -55C to +125C 2.5 1/ Testing and other quality control techniques are

    32、used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assu

    33、red by characterization and/or design. 2/ Unless otherwise specified, VDD= 15 V 10%, VSS= -15V 10%, VL= 5 V 10%, and GND = 0 V. 3/ Guaranteed by design, not subject to production test. 4/ Unless otherwise specified, VDD= 12 V 10%, VSS= 0 V, VL= 5 V 10%, and GND = 0 V. Provided by IHSNot for ResaleNo

    34、 reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/10615 REV PAGE 9 Case X FIGURE 1. Case outline. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND A

    35、ND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/10615 REV PAGE 10 Case X - continued. Symbol Dimensions Inches Millimeters Min Max Min Max A - 0.043 - 1.10 A1 0.029 0.037 0.75 0.95 A2 0.000 0.005 0.00 0.15 b 0.009 0.015 0.25 0.40 c 0.003 0.009 0.09 0.23 D 0.110 0.125 2.80 3.20 E 0

    36、.110 0.125 2.80 3.20 E1 0.183 0.202 4.65 5.15 e 0.025 BSC 0.65 BSC L 0.015 0.031 0.40 0.80 NOTES: 1. Controlling dimensions are millimeter, inch dimensions are given for reference only. 2. Falls with JEDEC MO-187-AA. FIGURE 1. Case outline - Continued. Provided by IHSNot for ResaleNo reproduction or

    37、 networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/10615 REV PAGE 11 Device type 01 Case outline X Terminal number Terminal symbol Description 1 D Drain terminal. May be an input or an output. 2 S1 Source terminal. May be a

    38、n input or an output. 3 GND Ground (0 V) reference. 4 VDDMost positive power supply potential. 5 VLLogic power supply (5 V). 6 IN Logic control input. 7 VSSMost negative power supply potential in dual-supply applications. In single-supply applications, it may be connected to GND. 8 S2 Source termina

    39、l. May be an input or an output. FIGURE 2. Terminal connections. Logic Switch 1 Switch 2 0 On Off 1 Off On FIGURE 3. Truth table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO.

    40、 V62/10615 REV PAGE 12 FIGURE 4. On resistance test circuit. FIGURE 5. Off leakage test circuit. FIGURE 6. On leakage test circuit. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG N

    41、O. V62/10615 REV PAGE 13 FIGURE 7. Transition time test circuit and waveforms. FIGURE 8. Break-before-make time delay test circuit and waveforms. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT N

    42、O. 16236 DWG NO. V62/10615 REV PAGE 14 FIGURE 9. Off isolation test circuit. Channel-to-channel crosstalk = 20 x log | VS/ VOUT| FIGURE 10. Crosstalk test circuit. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO S

    43、IZE A CODE IDENT NO. 16236 DWG NO. V62/10615 REV PAGE 15 4. VERIFICATION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicated in their internal documentation. Such procedures should include proper handling of electrostat

    44、ic sensitive devices, classification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPARATION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturers standard commercial practices for electrostatic discharg

    45、e sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturers data book. The device manufacturer reserves the r

    46、ight to make changes without notice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of present or continued availability as a source of supply for the item. Ven

    47、dor item drawing administrative control number 1/ Device manufacturer CAGE code Vendor part number V62/10615-01XA 24355 ADG419SRMZ-EP-RL7 1/ The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation. CAGE code Source of supply 24355 Analog Devices Route 1 Industrial Park P.O. Box 91


    注意事项

    本文(DLA DSCC-VID-V62 10615-2010 MICROCIRCUIT LINEAR CMOS SPDT SWITCH MONOLITHIC SILICON.pdf)为本站会员(eastlab115)主动上传,麦多课文档分享仅提供信息存储空间,仅对用户上传内容的表现方式做保护处理,对上载内容本身不做任何修改或编辑。 若此文所含内容侵犯了您的版权或隐私,请立即通知麦多课文档分享(点击联系客服),我们立即给予删除!




    关于我们 - 网站声明 - 网站地图 - 资源地图 - 友情链接 - 网站客服 - 联系我们

    copyright@ 2008-2019 麦多课文库(www.mydoc123.com)网站版权所有
    备案/许可证编号:苏ICP备17064731号-1 

    收起
    展开