BS EN 61188-1-2-1998 Printed boards and assemblies - Design and use - Generic requirements - Generic requirements - Controlled impedance《印制电路板及组件 设计和使用 一般要求 受控阻抗》.pdf

《BS EN 61188-1-2-1998 Printed boards and assemblies - Design and use - Generic requirements - Generic requirements - Controlled impedance《印制电路板及组件 设计和使用 一般要求 受控阻抗》.pdf》由会员分享，可在线阅读，更多相关《BS EN 61188-1-2-1998 Printed boards and assemblies - Design and use - Generic requirements - Generic requirements - Controlled impedance《印制电路板及组件 设计和使用 一般要求 受控阻抗》.pdf（38页珍藏版）》请在麦多课文档分享上搜索。

1、BRITISH STANDARD BS EN 61188-1-2:1998 IEC 61188-1-2: 1998 Printed boards and printed board assemblies Design and use Part 1-2: Generic requirements Controlled impedance The European Standard EN61188-1-2:1998 has the status of a British Standard ICS 31.180BSEN61188-1-2:1998 This British Standard, hav

2、ing been prepared under the direction of the Electrotechnical Sector Committee, was published under the authority of the Standards Committee and comes into effect on 15 December 1998 BSI 05-1999 ISBN 0 580 30658 5 National foreword This British Standard is the English language version of EN61188-1-2

3、:1998. It is identical with IEC61188-1-2:1998. The UK participation in its preparation was entrusted to Technical Committee EPL/501, Electrical assembly technology, which has the responsibility to: aid enquirers to understand the text; present to the responsible international/European committee any

4、enquiries on the interpretation, or proposals for change, and keep the UK interests informed; monitor related international and European developments and promulgate them in the UK. A list of organizations represented on this committee can be obtained on request to its secretary. From1 January1997, a

5、ll IEC publications have the number60000 added to the old number. For instance, IEC27-1 has been renumbered as IEC60027-1. For a period of time during the change over from one numbering system to the other, publications may contain identifiers from both systems. Cross-references Attention is drawn t

6、o the fact that CEN and CENELEC standards normally include an annex which lists normative references to international publications with their corresponding European publications. The British Standards which implement these international or European publications may be found in the BSI Standards Cata

7、logue under the section entitled “International Standards Correspondence Index”, or by using the “Find” facility of the BSI Standards Electronic Catalogue. A British Standard does not purport to include all the necessary provisions of a contract. Users of British Standards are responsible for their

8、correct application. Compliance with a British Standard does not of itself confer immunity from legal obligations. Summary of pages This document comprises a front cover, an inside front cover, pages i and ii, theENtitlepage, pages2 to33 and a back cover. This standard has been updated (see copyrigh

9、t date) and may have had amendments incorporated. This will be indicated in the amendment table on the inside front cover. Amendments issued since publication Amd. No. Date CommentsBSEN61188-1-2:1998 BSI 05-1999 i Contents Page National foreword Inside front cover Foreword 2 Text of EN 61188-1-2 3ii

10、 blankEUROPEAN STANDARD NORME EUROPENNE EUROPISCHE NORM EN61188-1-2 August1998 ICS31.180 English version Printed boards and printed board assemblies Design and use Part 1-2: Generic requirements Controlled impedance (IEC 61188-1-2:1998) Cartes imprimes et cartes imprimes quipes Conception et utilisa

11、tion Partie 1-2: Prescriptions gnriques Impdance contrle (CEI61188-1-2:1998) Leiterplatten und Flachbaugruppen Konstruktion und Anwendung Teil 1-2: Allgemeine Anforderungen Definierte Impedanz (IEC61188-1-2:1998) This European Standard was approved by CENELEC on1998-08-01. CENELEC members are bound

12、to comply with the CEN/CENELEC Internal Regulations which stipulate the conditions for giving this European Standard the status of a national standard without any alteration. Up-to-date lists and bibliographical references concerning such national standards may be obtained on application to the Cent

13、ral Secretariat or to any CENELEC member. This European Standard exists in three official versions (English, French, German). A version in any other language made by translation under the responsibility of a CENELEC member into its own language and notified to the Central Secretariat has the same st

14、atus as the official versions. CENELEC members are the national electrotechnical committees of Austria, Belgium, CzechRepublic, Denmark, Finland, France, Germany, Greece, Iceland, Ireland, Italy, Luxembourg, Netherlands, Norway, Portugal, Spain, Sweden, Switzerland and UnitedKingdom. CENELEC Europea

15、n Committee for Electrotechnical Standardization Comit Europen de Normalisation Electrotechnique Europisches Komitee fr Elektrotechnische Normung Central Secretariat: rue de Stassart 35, B-1050 Brussels 1998 CENELEC All rights of exploitation in any form and by any means reserved worldwide for CENEL

16、EC members. Ref. No. EN61188-1-2:1998 EEN61188-1-2:1998 2 BSI 05-1999 Foreword The text of document52/758/FDIS, future edition1 of IEC61188-1-2, prepared by IEC TC52, Printed circuits, was submitted to the IEC-CENELEC parallel vote and was approved by CENELEC as EN61188-1-2 on1998-08-01. The followi

17、ng dates were fixed: Annexes designated “normative” are part of the body of the standard. Annexes designated “informative” are given for information only. In this standard, Annex ZA is normative and Annex A is informative. Annex ZA has been added by CENELEC. Endorsement notice The text of the Intern

18、ational Standard IEC61188-1-2:1998 was approved by CENELEC as a European Standard without any modification. Contents Page Foreword 2 Introduction 3 1 Scope 3 2 Normative references 3 3 Engineering design overview 3 3.1 Device selection 3 3.2 Intraconnection 4 3.3 Printed board and printed board asse

19、mblies 5 3.4 Performance requirements 6 3.5 Power distribution 14 4 Design of controlled impedance circuits 14 4.1 Configurations 15 4.2 Equations 15 4.3 Controlled impedance design rules 19 4.4 Cross-talk rules 19 4.5 Coupon design rules 20 Page 4.6 Decoupling/capacitor rules 22 5 Design for manufa

20、cturing 23 5.1 Process rules in CAD 23 5.2 Design complexity and correlation to cost 24 6 Data description 24 6.1 Details of construction 24 6.2 Isolation of data by net class (noise, timing, capacitance and impedance) 25 6.3 Electrical performance 25 7 Material 25 7.1 Resin systems 25 7.2 Reinforce

21、ments 25 7.3 Prepregs, bonding layers and adhesives 26 7.4 Frequency dependence. 26 8 Fabrication 26 8.1 General 26 8.2 Preproduction processes 27 8.3 Production processes 29 8.4 Impact of defects at high frequencies 30 8.5 Data description 32 9 Time domain reflectometry (TDR) testing 32 9.1 Rationa

22、le 32 Annex A (informative) Units, symbols, andterminology 33 Annex ZA (normative) Normative references to international publications with their corresponding European publications 33 Figure 1 Switching speed versus propagation delay 6 Figure 2 ” rversus frequency (epoxide/glass laminate) 7 Figure 3

23、 Termination of nets 12 Figure 4 Surface microstrip 15 Figure 5 Embedded microstrip 16 Figure 6 Symmetric stripline 17 Figure 7 Dual (asymmetric) stripline 17 Figure 8 Wire stripline 18 Figure 9 Wire microstrip 18 Figure 10 Controlled impedance test coupon 21 Figure 11 Controlled impedance coupon pr

24、obe pattern 22 Table 1 Device rise time 8 Table 2 Typical data for some logic families 9 latest date by which the EN has to be implemented at national level by publication of an identical national standard or by endorsement (dop) 1999-05-01 latest date by which the national standards conflicting wit

25、h the EN have to be withdrawn (dow) 2001-05-01EN61188-1-2:1998 BSI 05-1999 3 Introduction Packaging of electronic equipment has traditionally been an area for mechanical considerations. Packaging design is becoming more complex as todays electronics technologies are available in greater switching sp

26、eed and higher density per chip. Individual chips have greater numbers of connections in smaller chip package sizes. To take maximum advantage of device density and speed, designers must pay much more attention to problems of electromagnetic wave propagation phenomena associated with transmission of

27、 switching signals within the system. New design disciplines and design strategies are needed. Controlled impedance printed boards are a part of this strategy. Interconnection and the packaging of electronic components primarily have been the domain of mechanical designers who were concerned with su

28、ch factors as weight, volume, power, and form factor and with interconnections specified in wire listing or net lists. Electrical conductors for signal transmission were routed with only a few concerns, that continuity was maintained between points, conductors had sufficient copper for the current a

29、nd clearance was maintained to prevent voltage breakdown. Aside from providing a good electrical path, the electrical performance of the signal was not a major concern. Advances in digital integrated circuits introduce new devices with extremely fast rise times which are housed in high density micro

30、electronic packages. In order to optimize system performance, these devices require a wiring technology that supports high density interconnection and, at the same time, provides superior electrical performance. While many system problems are associated with high speed digital processing, none has r

31、eceived more attention than interconnection. It is evident that as system speeds increase, interconnection, packaging, and printed boards become the bottlenecks that slow system performance. Systems using100K ECL circuitry have almost55% of the system delay in the packaging and interconnect. CMOS is

32、 normally considered a “slow” technology, but is designed into system clock rates in excess of100MHz. In these cases, not only is system delay a problem but signal attenuation becomes an issue with the low powered, low voltage, lower noise margin BiCMOS devices. 1 Scope This part of IEC61188 is inte

33、nded to be used by circuit designers, packaging engineers, printed board manufacturers and procurement personnel so that all may have a common understanding of each area. The aim in packaging is to transfer a signal from one device to one or more other devices through a conductor. High-speed designs

34、 are defined as designs in which the interconnecting properties affect circuit performance and require unique considerations. 2 Normative references The following normative documents contain provisions which, through reference in this text, constitute provisions of this part of IEC61188. At the time

35、 of publication, the editions indicated were valid. All normative documents are subject to revision, and parties to agreements based on this part of IEC61188 are encouraged to investigate the possibility of applying the most recent editions of the normative documents listed below. Members of IEC and

36、 ISO maintain registers of currently valid international standards. IEC61182 (all parts), Printed boards Electronic data description and transfer. IEC61182-1:1994, Printed boards Electronic data description and transfer Part 1: Printed board description in digital form. IEC61189-3:1997, Test methods

37、 for electrical materials, interconnection structures and assemblies Part3: Test methods for interconnection structures (printed boards). 3 Engineering design overview 3.1 Device selection Device technology options include TTL, Schottky TTL, CMOS, ECL and GaAs, each with its own set of power require

38、ments, operating temperature range, density of chip, input impedance, output impedance, signal threshold levels, noise sensitivity, response time and output pulse rise/fall time. Many designs will have mixed technology where SMT and through hole packaging is intermixed with TTL, CMOS and ECL logic t

39、hat may require multiple line widths (impedance values) on the same circuit layer or may compromise on a single conductor width that can provide enough margin for the different logic families.EN61188-1-2:1998 4 BSI 05-1999 Chips can be individually mounted on a large board or assembled into small bo

40、ards or multichip modules mounted onto large boards. Large systems may require several large board assemblies with another level of interconnection. Noise, timing, and signal degradation will accompany transitions from one packaging level to the next. The electrical connections to the board can be o

41、f a variety of configurations ranging from pins that will insert through plated holes in the board, as in dual in-line packages, to a series of lands for surface mount devices. Requirements for component packaging are dependent on many factors including space, economics, electrical performance and r

42、eliability, as well as the predominant packaging style of the assembly. The components shall be provided in a style that is compatible with the assembly processes used to manufacture the printed board assembly. The component package shall be considered when designing for high speed. In passive compo

43、nents the predominant factor will be the lead length as leads provide additional inductance and capacitance that will affect propagation speed and switching transients. To minimize these effects the leads may be as short as possible or removed. Surface mount devices can provide leadless packages whi

44、ch can be directly mounted to the interconnecting substrate. NOTEComponent data sheets often do not provide parasitic values for high speed noise and propagation speed consideration. Active devices, components such as integrated circuits, are often offered in several packages. In general, DIP packag

45、es, in either plastic or ceramic, have been the predominate package. These are typically the largest packages and provide the poorest high speed operating environment due to lead configuration. The next best package style is the surface mount package. These are offered in a variety of packages such

46、as SOICs, PLCCs, PFQPs, TSOPs BGAs. These packages will typically reduce the lead capacitance and inductance. To obtain the optimum performance from the device, the die can be directly mounted to the substrate using either the chip-on-board (COB), flip chip or tape automated bonding (TAB) approach.

47、These offer an optimum approach since they minimize the lead capacitance/inductance. 3.2 Intraconnection 3.2.1 Connectors Intraconnections are often troublesome in high speed application because a continuous signal environment is not provided. Most board to board connector systems are not designed f

48、or use in high performance applications and compromise the signal integrity of the system. Board to board connections often mismatch the characteristic impedance designed into the board themselves. There are two primary approaches to reduce the signal discontinuity caused by interconnect systems: a)

49、 The first approach is to provide a connector style such that the pinouts can be arranged to provide a good signal path. Non-differential signals shall establish a relationship between the active signal line and the closest reference plane connection, either a voltage or ground plane. Non-differential signal conductors rely on controlled geometries and nearby reference plane for impedance control. Signal pin quality, reference pin quality and their location controls electrical performance. To optimise performa