ATIS T1 TR 48-1996 Test Patterns for DS0 Synchronous Digital Data Circuits (SDD).pdf

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1、Report No. 48 A Technical ReportonJune 1996 Test Patterns for DS0Synchronous DigitalData Circuits (SDD)Prepared byT1M1.3Working Groupon Digital OAM transmission faults may takeupwards of 24 hours.5.0 LOOPBACK AND STRAIGHTAWAYTwo techniques are used for testing SDD services for transmission and equip

2、ment problems; loopback and straightaway.45.1 Loopback testingMost SDD services are designed to make use of remote circuit and element testing.Remote testing of SDD is accomplished by inserting test equipment into the circuit andthen sending specific loopback codes or control signals towards downstr

3、eam elements.When the element that has been addressed responds to this remote signal, it goes intoa loopback mode. Loopback is defined as “a state of a transmission facility in whichthe received signal is returned towards the sender”. Once an element has been placedinto the loopback state, the remot

4、e test equipment can transmit patterns of datatowards the element, and can then compare, on a bit-by-bit basis, what was received(looped back) to what was sent.The value of loopback testing is in the speed of the test. In a circuit failure situation,the application of test equipment into the circuit

5、; the operation of loopback devices inboth the network and the end users equipment; and the use of test patterns to validatethe circuit conditions; together provide a rapid method of trouble isolation.Two forms of loopback are in use; latching and non-latching (alternating). With latching loopback,

6、a loopback signal is transmitted in every byte for a set number of bytes. A successful loopback is detected when multiple “confirmation” bytes are received from the loop by the test set; test data is then analyzed for every DS0 byte. The loopback is released by sending a release sequence. Alternatin

7、g loopbacks are established by continually transmitting the specific loopback code in every other byte. Test data is then inserted in the remaining alternating bytes. Performing alternating loopbacks reduces the test rate by 50% since only half the data stream is being analyzed. It should be recogni

8、zed that there are cases where loopback testing can provide a falseindication of element condition. With alternating non-latching loopbacks, the test setmust synchronize with the alternating byte operation or a bit may be altered or droppedproviding faulty error counts having nothing to do with the

9、transmission circuit. Themisuse of the low-level loopback provided by the CSU may also cause faulty errorcounts. This “channel loopback” is applied behind the channel service unit at a point inthe circuit where logic processing is minimal. The possible automatic insertion of a onecan occur should th

10、e test pattern contain an excess of zeros. In addition, if a quick testof the CSU loopback is successful using only the basic PRBS or QRS patterns, it caneasily mask a higher level problem such as a lack of network synchronization orexcessive jitter. For this reason, synchronization and jitter tests

11、 should only beperformed with straightaway testing.A general guideline for the testing of SDD services is that loopback testing shouldalways be performed using the appropriate pseudorandom pattern, followed by morestressful fixed pattern test sequences.5.2 Straightaway testingStraightaway testing di

12、ffers from loopback testing in that it makes use of two test units.One example of this type of testing is the frequently performed acceptance testing fromthe end-user location to a remote test center. The value of this straightaway testing isthat it more closely resembles the actual use of the circu

13、it. Both ends of the circuit are5generating data in the form of known test patterns and both units must be synchronizedto the network timing and to each other.While straightaway testing can be performed between any two points in the circuit,attention to test equipment setup is critical. For example,

14、 if the test is to be run fromthe OCU to the Network Interface, one unit must be configured to replicate D-NCTEsuch as the CSU and the DSU while the other is configured to replicate a networkelement.6.0 TEST PATTERNSPseudorandom test patterns for SDD circuits are designed to be used to simulate live

15、data traffic to detect non-pattern sensitive impairments. Some patterns are effective for“stressing“ the timing recovery and equalization of line repeaters, OCUs andregenerating equipment. Others are designed to replicate actual data patterns, to testthe transmission path for what is referred to as

16、“protocol sensitivity.“ Pattern testingcan also detect mis-optioned equipment.7.0 STANDARD AND NOF SUPPORTED TEST PATTERNSThe test patterns identified in this section are those in the signal constellationrecommended by the Network Operations Forum (NOF) 4. In addition, these patternsare specified fo

17、r use in ANSI Standard T1.510-1994. (Note: Action is underway toprepare a supplement to ANSI T1.510-1994 3 changing the direction of transmissonfor the patterns specified in Annex B. In the original Annex B, the patterns weredesignated as being transmitted left-to-right LtR; they should be specified

18、 as beingtransmitted right-to-left RtL because the binary displays have not been reversed asdiscussed in clause 7.2 of this report).7.1 Pseudorandom (PRBS) and quasirandom (QRS) test patternsPseudorandom binary sequences (PRBS) can be generated using a simple shiftregister with specific feedback alg

19、orithms. Quasirandom (QRS) test patterns are PRBSartificially constrained to limit the number of consecutive “zeros” that can occur. BothPRBS and QRS patterns can be used to verify continuity between two points on acircuit and to check the circuits initial reaction to traffic. These patterns test ar

20、epeaters timing recovery and equalization circuitry. Timing recovery is tested by lowones density sections of the patterns and the equalization circuitry is stressed by thebroad frequency spectrum of the overall pattern.7.1.1 511-bit patternTwo versions of this pattern are currently in use in the in

21、dustry. One is theconventional PRBS; the second a QRS developed by modification of the PRBS testsequence to avoid transmitting more than seven consecutive zero-bits. The secondpattern, the QRS, is the defined pattern for testing 56 kbit/s with secondary channelwhen testing both channels simultaneous

22、ly 5.67.1.1.1 511-bit PRBSA 29-1 pattern with a maximum of 8 sequential zeroes and 9 sequential ones and iscompatible with CCITT2O.152 7.7.1.1.2 511-bit QRSA 29-1 pattern with a maximum of 7 sequential zeroes and 9 sequential ones. It iscompatible with CCITT O.152. This pattern is derived from the 5

23、11-bit PRBS modifiedby forcing the signal to “1” whenever the next seven bits of the sequence are all zeros.7.1.2 2047-bit patternsTwo versions of this pattern are currently in use in the industry. One is theconventional PRBS; the second a QRS developed by modification of the PRBS testsequence to av

24、oid transmission of more than seven consecutive zero-bits. The secondpattern, the QRS, is the defined pattern for testing 56 kbit/s with secondary channelwhen testing both channels simultaneously.7.1.2.1 2047-bit PRBSA 211-1 pattern with a maximum of 10 sequential zeroes and 11 sequential ones. It i

25、s compatible with CCITT O.152.7.1.2.2 2047-bit QRSThis is a 211-1 pattern with a maximum of 7 sequential zeroes and 11 sequential ones.It is compatible with CCITT O.152. This pattern is derived from the 2047-bit PRBSmodified by forcing the signal to “1” whenever the next seven bits of the sequence a

26、reall zeros.7.2 DS0 fixed patterns for pattern sensitivity testingThe fixed patterns in this section are binary representations of hexadecimal (hex)symbols. Hex symbols written in binary form are always transmitted least-significant bit(LSB) first. The 8-bits in each T-Carrier channel (DS0) are alwa

27、ys transmitted most-significant bit (MSB) first and, unless otherwise indicated, the order of bit transmissionis from left-to-right (LtR). As this is not always clearly understood, all test sets may notbe compatible.For the purposes of this technical report, the binary equivalent of the hex symbols

28、inthis section, when formatted for transmission, have been written in reverse order withthe order of bit transmission conforming with the T-Carrier rule - LtR., e.g. in DS0 3,hex 32hex(0011 0010) is written as 01001100 (LtR) rather than 00110010 (RtL).7.2.1 DS0 pattern one (DS0 1)This pattern, also

29、known as DDS 1, is a repeating pattern of FFhex(1111 1111)followed by 00hex(0000 0000) as follows:2CCITT is now known as ITU-T. Recommendations issued under the CCITT banner will eventually be reissuedas ITU-T Recommendations7BIT TRANSMISSIONORDER11111111 (LtR) repeated 100 times followed by00000000

30、 (LtR) repeated 100 timesThis combination of minimum and maximum densities causes the maximum stressingof SDD signal recovery circuitry.7.2.2 DS0 pattern two (DS0 2)This pattern is also known as DDS 2, and is a repeating pattern of 7Ehex (0111 1110)followed by 00hex( 0000 0000) as follows:BIT TRANSM

31、ISSIONORDER01111110 (LtR) repeated 100 times followed by00000000 (LtR) repeated 100 timesIn addition to providing a minimum ones density stress, this pattern is similar to bitoriented protocol characters called “flag bytes.“ These bytes are common in X.25,X.75, SDLC, SNA, HDLC AND SS7 protocols.7.2.

32、3 DS0 pattern three (DS0 3)This pattern is also known as DDS 3, and is a continuous series of 32hex(0011 0010)as follows:BIT TRANSMISSIONORDER01001100 (LtR) repeated 200 timesThis represents an “average“ of typical SDD traffic patterns, especially in the BisyncEBCDIC protocol. This pattern mimics th

33、e sub-rate framing patterns for 2.4 & 4.8 kbitsoperations.7.2.4 DS0 pattern four (DS0 4)This pattern is also known as DDS 4 and 1-in-7 and is a continuous series of40hex(0100 0000) as follows:BIT TRANSMISSIONORDER00000010 (LtR) repeated 200 timesIt is a useful low 1s density pattern, and is characte

34、ristic of DEC VT traffic.87.2.5 DS0 pattern five (DS0 5)This is also known as DDS 5, and it is not so much a distinctive pattern as it is anapplication of the patterns DS0 1, 2, 3 and 4 transmitted LtR sequentially for a total of2000 bytes as follows:100 bytes of 11111111 (DDS 1)100 bytes of 0000000

35、0100 bytes of 11111111100 bytes of 00000000100 bytes of 11111111100 bytes of 00000000100 bytes of 11111111100 bytes of 00000000100 bytes of 01111110 (DDS 2)100 bytes of 00000000100 bytes of 01111110100 bytes of 00000000100 bytes of 01111110100 bytes of 00000000100 bytes of 01111110100 bytes of 00000

36、000200 bytes of 01001100 (DDS 3)200 bytes of 00000010 (DDS 4)When this pattern is available in test equipment, it automates the sending of DS0patterns 1-4, and can reduce the time required to perform circuit testing.8.0 OTHER USEFUL PATTERNSThese patterns, while not recognized by existing standards

37、or industry agreements,have been used and may prove useful in revealing (potential) deficiencies not observedby testing with the above patterns. The lack of industry agreement may cause a lack ofavailability in some test equipment, however, they can be used in the loopback mode ifprovided by the tes

38、t equipment.8.1 CMI/DMI transition test patternThis pattern is sometimes referenced as DS0 6 (DDS 6) and consists of 7Fhex(0111 1111) repeated 7 times followed by a single byte of FFhex(1111 1111) asfollows:BIT TRANSMISSIONORDER11111110 (LtR) repeated 7-times followed by11111111 (LtR) transmitted on

39、ce9This pattern provides a test of the transistion from the Control Mode Idle (CMI)condition to the Data Mode Idle (DMI) condition and must be byte aligned in a full64 kbit/s DS0 channel.The transition from Control Mode Idle (CMI) to Data Mode Idle (DMI) is used to detect marginal equipment in a mul

40、ti-station network environment.8.2 215-1 PRBS test pattern (inverted)3A more random pattern than the 511 and 2047 patterns. This is compatible with CCITTO.1516, and is recommended for rates above 19.2 kbit/s w/o secondary channel. Thepattern has a maximum of 15 sequential zeros and 14 sequential one

41、s, making this auseful test for 64 kbit/s clear channel circuits.8.3 220-1 QRS test patternA quasirandom pattern used in ITU-T comprised of a maximum of 14 sequential zerosand 20 sequential ones described in IEEE Standard 1007 10. The output bit is forcedto be a “one” whenever the next 14 bits are a

42、ll “zero”.8.4 223-1 test pattern (inverted)3A pseudorandom pattern containing a maximum of 23 sequential zeros followed by22 sequential ones described in IEEE Standard 1007. If non-inverted, the patternwould contain a maximum of 22 sequential “zeros” and 23 sequential “ones”.8.5 Digital reference si

43、gnal (DRS)The DRS is a new 797-byte dual use digital pattern, described in IEEE Standard743-1995 9 and referenced in ANSI T1.207a 1. The DRS, when decoded with an8-bit digital-to-analog (D/A) converter, provides a 1013.8 Hz tone for analog measurements. When placed on a circuit in its digital format

44、, it provides a specific repetitive digital sequence useful for circuit continuity and bit error ratio testing. The DRS analog frequency when converted with an 8-bit D-A converter is 101/8000 = 1013.801757 Hz. The DRS encoding formula is:V(N)= 8159 (10-3.17/20) sin (K (N-1) where K = 202pi/797 and N

45、 is the byte number and the sampling rate is 8000 Hz. The 64 kbit/s digital signal must be byte aligned when converting from the digital to an analog signal.3The 215-1 and 223-1 PRBS inverted patterns are ITU-T (CCITT) patterns. IUT-T considers the invertedpatterns as being more stressful than non-i

46、nverted patterns when testing the clock recovery circuits in thenetwork terminating devices they were designed to test. The 220-1 QRS non-inverted pattern is specified fortesting North American 1.544 Mbit/s DS1 systems/equipment.109.0 RELATED STANDARDS AND PUBLICATIONS1 ANSI T1.207a-1995 Supplement

47、to T1.207-1989“Terminating Test Line Capabilities and Access Arrangements”2 ANSI T1.410-1992“Carrier-to-Customer Metallic Interface -Digital Data at 64 kbit/s and Subrates“3 ANSI T1.510-1994“Network Performance Parameters forDedicated Digital Services - Specifications”4 NETWORK OPERATIONS FORUM REFE

48、RENCE DOCUMENT ISSUE 7, 11 February 1994, Section I ,“Installation and Maintenance Responsibilities, Special AccessServices, WATS Access Lines and Switched Access Services -Feature Group A”5 BELLCORE TR-NWT-000819, ISSUE 1, November 1992OTGR SECTION 6.2:“Network Maintenance: Access Testing - Special

49、 Services(SS) and SS-Like Services” (A Module of OTGR, FR-NWT-000439)6 ITU-T RECOMMENDATION O.151 October 1992.“Specifications of Measuring Equipment - Error PerformanceMeasuring Equipment Operating at the Primary Rate and Above”.7 ITU-T RECOMMENDATION O.152 October 1992.“Specifications of Measuring Equipment - Error PerformanceMeasuring Equipment for 64 Kbit/s Paths”.8 ITU-T RECOMMENDATION O.153 October 1992.“Specifications of Measuring Equipment - Basic Parametersfor the Measurement of Error Perfromance at Bit-Rates Belowthe Primary